Timing Analyzer report for siebensegDec
Thu Jun 01 15:33:04 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                          ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From     ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 12.039 ns   ; pin_name ; pin_name3 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;          ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F780C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------+
; tpd                                                                 ;
+-------+-------------------+-----------------+-----------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To        ;
+-------+-------------------+-----------------+-----------+-----------+
; N/A   ; None              ; 12.039 ns       ; pin_name  ; pin_name3 ;
; N/A   ; None              ; 11.759 ns       ; pin_name2 ; pin_name3 ;
; N/A   ; None              ; 11.621 ns       ; pin_name1 ; pin_name3 ;
; N/A   ; None              ; 11.463 ns       ; pin_name  ; pin_name6 ;
; N/A   ; None              ; 11.460 ns       ; pin_name  ; pin_name8 ;
; N/A   ; None              ; 11.460 ns       ; pin_name  ; pin_name7 ;
; N/A   ; None              ; 11.457 ns       ; pin_name  ; pin_name5 ;
; N/A   ; None              ; 11.418 ns       ; pin_name2 ; pin_name9 ;
; N/A   ; None              ; 11.418 ns       ; pin_name  ; pin_name4 ;
; N/A   ; None              ; 11.275 ns       ; pin_name1 ; pin_name9 ;
; N/A   ; None              ; 11.183 ns       ; pin_name2 ; pin_name8 ;
; N/A   ; None              ; 11.183 ns       ; pin_name2 ; pin_name6 ;
; N/A   ; None              ; 11.180 ns       ; pin_name2 ; pin_name7 ;
; N/A   ; None              ; 11.139 ns       ; pin_name2 ; pin_name4 ;
; N/A   ; None              ; 11.045 ns       ; pin_name1 ; pin_name6 ;
; N/A   ; None              ; 11.038 ns       ; pin_name1 ; pin_name5 ;
; N/A   ; None              ; 11.037 ns       ; pin_name1 ; pin_name8 ;
+-------+-------------------+-----------------+-----------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 01 15:33:03 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off siebensegDec -c siebensegDec --timing_analysis_only
Info: Longest tpd from source pin "pin_name" to destination pin "pin_name3" is 12.039 ns
    Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_W5; Fanout = 5; PIN Node = 'pin_name'
    Info: 2: + IC(5.923 ns) + CELL(0.459 ns) = 7.677 ns; Loc. = LC_X9_Y30_N5; Fanout = 2; COMB Node = 'siebensegmentdecodermzwo:inst|inst4~13'
    Info: 3: + IC(1.858 ns) + CELL(2.504 ns) = 12.039 ns; Loc. = PIN_B18; Fanout = 0; PIN Node = 'pin_name3'
    Info: Total cell delay = 4.258 ns ( 35.37 % )
    Info: Total interconnect delay = 7.781 ns ( 64.63 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Jun 01 15:33:04 2006
    Info: Elapsed time: 00:00:01


