Timing Analyzer report for eisenbahn_automat
Thu Jun 29 15:27:57 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'altpll0:inst26|altpll:altpll_component|_clk0'
  6. Clock Hold: 'altpll0:inst26|altpll:altpll_component|_clk0'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                       ;
+-------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Type                                                        ; Slack       ; Required Time                     ; Actual Time                                    ; From                           ; To                             ; From Clock                                   ; To Clock                                     ; Failed Paths ;
+-------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Worst-case tsu                                              ; N/A         ; None                              ; 1.066 ns                                       ; DEP_IN2                        ; eisenbahn_automat:inst1|inst36 ; --                                           ; PLD_CLOCKINPUT                               ; 0            ;
; Worst-case tco                                              ; N/A         ; None                              ; 12.979 ns                                      ; eisenbahn_automat:inst1|inst37 ; LED6                           ; PLD_CLOCKINPUT                               ; --                                           ; 0            ;
; Worst-case tpd                                              ; N/A         ; None                              ; 11.844 ns                                      ; BTN1                           ; LED7                           ; --                                           ; --                                           ; 0            ;
; Worst-case th                                               ; N/A         ; None                              ; -0.079 ns                                      ; DEP_IN0                        ; eisenbahn_automat:inst1|inst37 ; --                                           ; PLD_CLOCKINPUT                               ; 0            ;
; Clock Setup: 'altpll0:inst26|altpll:altpll_component|_clk0' ; 3398.000 ns ; 0.29 MHz ( period = 3400.000 ns ) ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; eisenbahn_automat:inst1|inst37 ; eisenbahn_automat:inst1|inst36 ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altpll0:inst26|altpll:altpll_component|_clk0'  ; 0.527 ns    ; 0.29 MHz ( period = 3400.000 ns ) ; N/A                                            ; eisenbahn_automat:inst1|inst38 ; eisenbahn_automat:inst1|inst38 ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                ;             ;                                   ;                                                ;                                ;                                ;                                              ;                                              ; 0            ;
+-------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+----------------------------------------------+----------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F780C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                     ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                              ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on       ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------------+-----------------------+---------------------+-----------+--------------+
; altpll0:inst26|altpll:altpll_component|_clk0 ;                    ; PLL output ; 0.29 MHz         ; 0.000 ns      ; 0.000 ns     ; PLD_CLOCKINPUT ; 1                     ; 170                 ; -1.561 ns ;              ;
; PLD_CLOCKINPUT                               ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --             ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altpll0:inst26|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                       ;
+-------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack       ; Actual fmax (period)                          ; From                                                                                    ; To                                                                                      ; From Clock                                   ; To Clock                                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3398.000 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 1.536 ns                ;
; 3398.028 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.784 ns                ;
; 3398.028 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.784 ns                ;
; 3398.028 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.784 ns                ;
; 3398.028 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.784 ns                ;
; 3398.028 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.784 ns                ;
; 3398.033 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.779 ns                ;
; 3398.033 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.779 ns                ;
; 3398.033 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.779 ns                ;
; 3398.033 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.779 ns                ;
; 3398.033 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.779 ns                ;
; 3398.083 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.729 ns                ;
; 3398.083 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.729 ns                ;
; 3398.083 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.729 ns                ;
; 3398.083 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.729 ns                ;
; 3398.083 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.729 ns                ;
; 3398.087 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 1.449 ns                ;
; 3398.089 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 1.447 ns                ;
; 3398.090 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.722 ns                ;
; 3398.090 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.722 ns                ;
; 3398.090 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.722 ns                ;
; 3398.090 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.722 ns                ;
; 3398.090 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.722 ns                ;
; 3398.200 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 1.336 ns                ;
; 3398.231 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.581 ns                ;
; 3398.231 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.581 ns                ;
; 3398.231 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.581 ns                ;
; 3398.231 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.581 ns                ;
; 3398.231 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.812 ns               ; 1.581 ns                ;
; 3398.276 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.538 ns                ;
; 3398.285 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.529 ns                ;
; 3398.287 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.527 ns                ;
; 3398.288 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.526 ns                ;
; 3398.338 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.476 ns                ;
; 3398.344 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.470 ns                ;
; 3398.344 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.470 ns                ;
; 3398.346 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.468 ns                ;
; 3398.347 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.467 ns                ;
; 3398.348 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.466 ns                ;
; 3398.349 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.465 ns                ;
; 3398.350 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.464 ns                ;
; 3398.406 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.408 ns                ;
; 3398.410 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.404 ns                ;
; 3398.411 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.403 ns                ;
; 3398.412 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.402 ns                ;
; 3398.436 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 1.100 ns                ;
; 3398.468 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.346 ns                ;
; 3398.472 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.342 ns                ;
; 3398.473 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.341 ns                ;
; 3398.474 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.340 ns                ;
; 3398.562 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 0.974 ns                ;
; 3398.669 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 0.867 ns                ;
; 3398.677 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 0.859 ns                ;
; 3398.792 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.022 ns                ;
; 3398.793 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.021 ns                ;
; 3398.799 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.015 ns                ;
; 3398.801 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.013 ns                ;
; 3398.802 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 1.012 ns                ;
; 3398.807 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.536 ns               ; 0.729 ns                ;
; 3398.905 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 0.909 ns                ;
; 3398.907 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 0.907 ns                ;
; 3398.911 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 0.903 ns                ;
; 3398.912 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 0.902 ns                ;
; 3398.913 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 3400.000 ns                 ; 3399.814 ns               ; 0.901 ns                ;
+-------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'altpll0:inst26|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                           ;
+---------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From                                                                                    ; To                                                                                      ; From Clock                                   ; To Clock                                     ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+---------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+----------------------------+----------------------------+--------------------------+
; 0.527 ns      ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 0.729 ns                 ;
; 0.657 ns      ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 0.859 ns                 ;
; 0.665 ns      ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 0.867 ns                 ;
; 0.759 ns      ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 0.961 ns                 ;
; 0.772 ns      ; eisenbahn_automat:inst1|inst36                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 0.974 ns                 ;
; 0.894 ns      ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 1.096 ns                 ;
; 0.895 ns      ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst37                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 1.097 ns                 ;
; 0.898 ns      ; eisenbahn_automat:inst1|inst37                                                          ; eisenbahn_automat:inst1|inst38                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 1.100 ns                 ;
; 0.960 ns      ; eisenbahn_automat:inst1|inst38                                                          ; eisenbahn_automat:inst1|inst36                                                          ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.202 ns                   ; 1.162 ns                 ;
; 0.977 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 0.901 ns                 ;
; 0.978 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 0.902 ns                 ;
; 0.979 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 0.903 ns                 ;
; 0.983 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 0.907 ns                 ;
; 0.985 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 0.909 ns                 ;
; 1.088 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.012 ns                 ;
; 1.089 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.013 ns                 ;
; 1.091 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.015 ns                 ;
; 1.097 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.021 ns                 ;
; 1.098 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.022 ns                 ;
; 1.403 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.327 ns                 ;
; 1.404 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.328 ns                 ;
; 1.405 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.329 ns                 ;
; 1.409 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.333 ns                 ;
; 1.463 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.387 ns                 ;
; 1.464 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.388 ns                 ;
; 1.465 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.389 ns                 ;
; 1.469 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.393 ns                 ;
; 1.519 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.443 ns                 ;
; 1.520 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.444 ns                 ;
; 1.522 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.446 ns                 ;
; 1.523 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.447 ns                 ;
; 1.524 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.448 ns                 ;
; 1.525 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.449 ns                 ;
; 1.528 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.452 ns                 ;
; 1.529 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.453 ns                 ;
; 1.579 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.503 ns                 ;
; 1.583 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.507 ns                 ;
; 1.584 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.508 ns                 ;
; 1.588 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.076 ns                  ; 1.512 ns                 ;
; 1.659 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.581 ns                 ;
; 1.659 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.581 ns                 ;
; 1.659 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.581 ns                 ;
; 1.659 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.581 ns                 ;
; 1.659 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.581 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.794 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.716 ns                 ;
; 1.851 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.773 ns                 ;
; 1.851 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.773 ns                 ;
; 1.851 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.773 ns                 ;
; 1.851 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.773 ns                 ;
; 1.851 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.773 ns                 ;
; 1.853 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.775 ns                 ;
; 1.853 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.775 ns                 ;
; 1.853 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.775 ns                 ;
; 1.853 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.775 ns                 ;
; 1.853 ns      ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2] ; lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5] ; altpll0:inst26|altpll:altpll_component|_clk0 ; altpll0:inst26|altpll:altpll_component|_clk0 ; 0.000 ns                   ; -0.078 ns                  ; 1.775 ns                 ;
+---------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------+
; tsu                                                                                           ;
+-------+--------------+------------+---------+--------------------------------+----------------+
; Slack ; Required tsu ; Actual tsu ; From    ; To                             ; To Clock       ;
+-------+--------------+------------+---------+--------------------------------+----------------+
; N/A   ; None         ; 1.066 ns   ; DEP_IN2 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 1.064 ns   ; DEP_IN2 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.959 ns   ; DEP_IN1 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.860 ns   ; DEP_IN3 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.858 ns   ; DEP_IN3 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.759 ns   ; DEP_IN1 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.709 ns   ; DEP_IN3 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.685 ns   ; DEP_IN2 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.672 ns   ; DEP_IN0 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.627 ns   ; DEP_IN4 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.625 ns   ; DEP_IN4 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.483 ns   ; DEP_IN4 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 0.467 ns   ; DEP_IN0 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
+-------+--------------+------------+---------+--------------------------------+----------------+


+------------------------------------------------------------------------------------------------+
; tco                                                                                            ;
+-------+--------------+------------+--------------------------------+----------+----------------+
; Slack ; Required tco ; Actual tco ; From                           ; To       ; From Clock     ;
+-------+--------------+------------+--------------------------------+----------+----------------+
; N/A   ; None         ; 12.979 ns  ; eisenbahn_automat:inst1|inst37 ; LED6     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.883 ns  ; eisenbahn_automat:inst1|inst38 ; LED6     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.660 ns  ; eisenbahn_automat:inst1|inst37 ; DEP_OUT2 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.582 ns  ; eisenbahn_automat:inst1|inst37 ; LED2     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.578 ns  ; eisenbahn_automat:inst1|inst37 ; LED4     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.406 ns  ; eisenbahn_automat:inst1|inst36 ; DEP_OUT2 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.327 ns  ; eisenbahn_automat:inst1|inst36 ; LED2     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 12.324 ns  ; eisenbahn_automat:inst1|inst36 ; LED4     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 11.636 ns  ; eisenbahn_automat:inst1|inst38 ; LED5     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 11.615 ns  ; eisenbahn_automat:inst1|inst38 ; LED3     ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 11.584 ns  ; eisenbahn_automat:inst1|inst37 ; DEP_OUT4 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 11.488 ns  ; eisenbahn_automat:inst1|inst38 ; DEP_OUT4 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 11.101 ns  ; eisenbahn_automat:inst1|inst38 ; DEP_OUT1 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 10.639 ns  ; eisenbahn_automat:inst1|inst36 ; DEP_OUT0 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 10.511 ns  ; eisenbahn_automat:inst1|inst37 ; DEP_OUT0 ; PLD_CLOCKINPUT ;
; N/A   ; None         ; 10.310 ns  ; eisenbahn_automat:inst1|inst38 ; DEP_OUT3 ; PLD_CLOCKINPUT ;
+-------+--------------+------------+--------------------------------+----------+----------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-------------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From        ; To       ;
+-------+-------------------+-----------------+-------------+----------+
; N/A   ; None              ; 11.844 ns       ; BTN1        ; LED7     ;
; N/A   ; None              ; 11.821 ns       ; PLD_CLEAR_N ; LED7     ;
; N/A   ; None              ; 10.580 ns       ; BTN0        ; LED1     ;
; N/A   ; None              ; 10.580 ns       ; BTN0        ; LED0     ;
; N/A   ; None              ; 10.429 ns       ; BTN0        ; DEP_OUT0 ;
+-------+-------------------+-----------------+-------------+----------+


+-----------------------------------------------------------------------------------------------------+
; th                                                                                                  ;
+---------------+-------------+-----------+---------+--------------------------------+----------------+
; Minimum Slack ; Required th ; Actual th ; From    ; To                             ; To Clock       ;
+---------------+-------------+-----------+---------+--------------------------------+----------------+
; N/A           ; None        ; -0.079 ns ; DEP_IN0 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.095 ns ; DEP_IN4 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.237 ns ; DEP_IN4 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.239 ns ; DEP_IN4 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.284 ns ; DEP_IN0 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.297 ns ; DEP_IN2 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.321 ns ; DEP_IN3 ; eisenbahn_automat:inst1|inst38 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.371 ns ; DEP_IN1 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.470 ns ; DEP_IN3 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.472 ns ; DEP_IN3 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.571 ns ; DEP_IN1 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.676 ns ; DEP_IN2 ; eisenbahn_automat:inst1|inst37 ; PLD_CLOCKINPUT ;
; N/A           ; None        ; -0.678 ns ; DEP_IN2 ; eisenbahn_automat:inst1|inst36 ; PLD_CLOCKINPUT ;
+---------------+-------------+-----------+---------+--------------------------------+----------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 29 15:27:55 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off eisenbahn_automat -c eisenbahn_automat --timing_analysis_only
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Found 24 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUTCOUT1_1" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[1]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUTCOUT1_1" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[2]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[3]" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[5]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella6~COUTCOUT1_1" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[6]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella7~COUTCOUT1_1" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella6~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[7]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella7~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[8]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUTCOUT1_1" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[4]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella8~COUTCOUT1_1" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella8~COUT" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella4~COUT" as buffer
    Info: Detected ripple clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9]" as buffer
    Info: Detected gated clock "lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT" as buffer
Info: Found timing assignments -- calculating delays
Info: Slack time is 3.398 us for clock "altpll0:inst26|altpll:altpll_component|_clk0" between source register "eisenbahn_automat:inst1|inst37" and destination register "eisenbahn_automat:inst1|inst36"
    Info: Fmax is restricted to 450.05 MHz due to tcl and tch limits
    Info: + Largest register to register requirement is 3399.536 ns
        Info: + Setup relationship between source and destination is 3400.000 ns
            Info: + Latch edge is 3398.439 ns
                Info: Clock period of Destination clock "altpll0:inst26|altpll:altpll_component|_clk0" is 3400.000 ns with  offset of -1.561 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -1.561 ns
                Info: Clock period of Source clock "altpll0:inst26|altpll:altpll_component|_clk0" is 3400.000 ns with  offset of -1.561 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is -0.278 ns
            Info: + Shortest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to destination register is 7.250 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.427 ns) + CELL(0.736 ns) = 2.163 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9]'
                Info: 3: + IC(0.439 ns) + CELL(0.551 ns) = 3.153 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
                Info: 4: + IC(0.000 ns) + CELL(0.472 ns) = 3.625 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
                Info: 5: + IC(3.065 ns) + CELL(0.560 ns) = 7.250 ns; Loc. = LC_X12_Y1_N5; Fanout = 6; REG Node = 'eisenbahn_automat:inst1|inst36'
                Info: Total cell delay = 2.319 ns ( 31.99 % )
                Info: Total interconnect delay = 4.931 ns ( 68.01 % )
            Info: - Longest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to source register is 7.528 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.429 ns) + CELL(0.736 ns) = 2.165 ns; Loc. = LC_X1_Y18_N5; Fanout = 3; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0]'
                Info: 3: + IC(0.413 ns) + CELL(0.344 ns) = 2.922 ns; Loc. = LC_X1_Y18_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella0~COUT'
                Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 2.982 ns; Loc. = LC_X1_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUT'
                Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 3.042 ns; Loc. = LC_X1_Y18_N7; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUT'
                Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.102 ns; Loc. = LC_X1_Y18_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUT'
                Info: 7: + IC(0.000 ns) + CELL(0.219 ns) = 3.321 ns; Loc. = LC_X1_Y18_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella4~COUT'
                Info: 8: + IC(0.000 ns) + CELL(0.110 ns) = 3.431 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
                Info: 9: + IC(0.000 ns) + CELL(0.472 ns) = 3.903 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
                Info: 10: + IC(3.065 ns) + CELL(0.560 ns) = 7.528 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
                Info: Total cell delay = 2.621 ns ( 34.82 % )
                Info: Total interconnect delay = 4.907 ns ( 65.18 % )
        Info: - Micro clock to output delay of source is 0.176 ns
        Info: - Micro setup delay of destination is 0.010 ns
    Info: - Longest register to register delay is 1.536 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
        Info: 2: + IC(0.630 ns) + CELL(0.332 ns) = 0.962 ns; Loc. = LC_X12_Y1_N6; Fanout = 1; COMB Node = 'eisenbahn_automat:inst1|inst16~153'
        Info: 3: + IC(0.339 ns) + CELL(0.235 ns) = 1.536 ns; Loc. = LC_X12_Y1_N5; Fanout = 6; REG Node = 'eisenbahn_automat:inst1|inst36'
        Info: Total cell delay = 0.567 ns ( 36.91 % )
        Info: Total interconnect delay = 0.969 ns ( 63.09 % )
Info: No valid register-to-register data paths exist for clock "PLD_CLOCKINPUT"
Info: Minimum slack time is 527 ps for clock "altpll0:inst26|altpll:altpll_component|_clk0" between source register "eisenbahn_automat:inst1|inst38" and destination register "eisenbahn_automat:inst1|inst38"
    Info: + Shortest register to register delay is 0.729 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N2; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst38'
        Info: 2: + IC(0.494 ns) + CELL(0.235 ns) = 0.729 ns; Loc. = LC_X12_Y1_N2; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst38'
        Info: Total cell delay = 0.235 ns ( 32.24 % )
        Info: Total interconnect delay = 0.494 ns ( 67.76 % )
    Info: - Smallest register to register requirement is 0.202 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -1.561 ns
                Info: Clock period of Destination clock "altpll0:inst26|altpll:altpll_component|_clk0" is 3400.000 ns with  offset of -1.561 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -1.561 ns
                Info: Clock period of Source clock "altpll0:inst26|altpll:altpll_component|_clk0" is 3400.000 ns with  offset of -1.561 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.278 ns
            Info: + Longest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to destination register is 7.528 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.429 ns) + CELL(0.736 ns) = 2.165 ns; Loc. = LC_X1_Y18_N5; Fanout = 3; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0]'
                Info: 3: + IC(0.413 ns) + CELL(0.344 ns) = 2.922 ns; Loc. = LC_X1_Y18_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella0~COUT'
                Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 2.982 ns; Loc. = LC_X1_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUT'
                Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 3.042 ns; Loc. = LC_X1_Y18_N7; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUT'
                Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.102 ns; Loc. = LC_X1_Y18_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUT'
                Info: 7: + IC(0.000 ns) + CELL(0.219 ns) = 3.321 ns; Loc. = LC_X1_Y18_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella4~COUT'
                Info: 8: + IC(0.000 ns) + CELL(0.110 ns) = 3.431 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
                Info: 9: + IC(0.000 ns) + CELL(0.472 ns) = 3.903 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
                Info: 10: + IC(3.065 ns) + CELL(0.560 ns) = 7.528 ns; Loc. = LC_X12_Y1_N2; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst38'
                Info: Total cell delay = 2.621 ns ( 34.82 % )
                Info: Total interconnect delay = 4.907 ns ( 65.18 % )
            Info: - Shortest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to source register is 7.250 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
                Info: 2: + IC(1.427 ns) + CELL(0.736 ns) = 2.163 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9]'
                Info: 3: + IC(0.439 ns) + CELL(0.551 ns) = 3.153 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
                Info: 4: + IC(0.000 ns) + CELL(0.472 ns) = 3.625 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
                Info: 5: + IC(3.065 ns) + CELL(0.560 ns) = 7.250 ns; Loc. = LC_X12_Y1_N2; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst38'
                Info: Total cell delay = 2.319 ns ( 31.99 % )
                Info: Total interconnect delay = 4.931 ns ( 68.01 % )
        Info: - Micro clock to output delay of source is 0.176 ns
        Info: + Micro hold delay of destination is 0.100 ns
Info: tsu for register "eisenbahn_automat:inst1|inst36" (data pin = "DEP_IN2", clock pin = "PLD_CLOCKINPUT") is 1.066 ns
    Info: + Longest pin to register delay is 6.745 ns
        Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_AA20; Fanout = 2; PIN Node = 'DEP_IN2'
        Info: 2: + IC(4.403 ns) + CELL(0.332 ns) = 5.876 ns; Loc. = LC_X12_Y1_N1; Fanout = 2; COMB Node = 'eisenbahn_automat:inst1|inst16~152'
        Info: 3: + IC(0.380 ns) + CELL(0.489 ns) = 6.745 ns; Loc. = LC_X12_Y1_N5; Fanout = 6; REG Node = 'eisenbahn_automat:inst1|inst36'
        Info: Total cell delay = 1.962 ns ( 29.09 % )
        Info: Total interconnect delay = 4.783 ns ( 70.91 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Offset between input clock "PLD_CLOCKINPUT" and output clock "altpll0:inst26|altpll:altpll_component|_clk0" is -1.561 ns
    Info: - Shortest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to destination register is 7.250 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
        Info: 2: + IC(1.427 ns) + CELL(0.736 ns) = 2.163 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[9]'
        Info: 3: + IC(0.439 ns) + CELL(0.551 ns) = 3.153 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.472 ns) = 3.625 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
        Info: 5: + IC(3.065 ns) + CELL(0.560 ns) = 7.250 ns; Loc. = LC_X12_Y1_N5; Fanout = 6; REG Node = 'eisenbahn_automat:inst1|inst36'
        Info: Total cell delay = 2.319 ns ( 31.99 % )
        Info: Total interconnect delay = 4.931 ns ( 68.01 % )
Info: tco from clock "PLD_CLOCKINPUT" to destination pin "LED6" through register "eisenbahn_automat:inst1|inst37" is 12.979 ns
    Info: + Offset between input clock "PLD_CLOCKINPUT" and output clock "altpll0:inst26|altpll:altpll_component|_clk0" is -1.561 ns
    Info: + Longest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to source register is 7.528 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
        Info: 2: + IC(1.429 ns) + CELL(0.736 ns) = 2.165 ns; Loc. = LC_X1_Y18_N5; Fanout = 3; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0]'
        Info: 3: + IC(0.413 ns) + CELL(0.344 ns) = 2.922 ns; Loc. = LC_X1_Y18_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella0~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 2.982 ns; Loc. = LC_X1_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUT'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 3.042 ns; Loc. = LC_X1_Y18_N7; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUT'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.102 ns; Loc. = LC_X1_Y18_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUT'
        Info: 7: + IC(0.000 ns) + CELL(0.219 ns) = 3.321 ns; Loc. = LC_X1_Y18_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella4~COUT'
        Info: 8: + IC(0.000 ns) + CELL(0.110 ns) = 3.431 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
        Info: 9: + IC(0.000 ns) + CELL(0.472 ns) = 3.903 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
        Info: 10: + IC(3.065 ns) + CELL(0.560 ns) = 7.528 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
        Info: Total cell delay = 2.621 ns ( 34.82 % )
        Info: Total interconnect delay = 4.907 ns ( 65.18 % )
    Info: + Micro clock to output delay of source is 0.176 ns
    Info: + Longest register to pin delay is 6.836 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
        Info: 2: + IC(1.150 ns) + CELL(0.213 ns) = 1.363 ns; Loc. = LC_X12_Y2_N2; Fanout = 2; COMB Node = 'eisenbahn_automat:inst1|inst34'
        Info: 3: + IC(2.978 ns) + CELL(2.495 ns) = 6.836 ns; Loc. = PIN_L20; Fanout = 0; PIN Node = 'LED6'
        Info: Total cell delay = 2.708 ns ( 39.61 % )
        Info: Total interconnect delay = 4.128 ns ( 60.39 % )
Info: Longest tpd from source pin "BTN1" to destination pin "LED7" is 11.844 ns
    Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_W6; Fanout = 1; PIN Node = 'BTN1'
    Info: 2: + IC(4.300 ns) + CELL(0.087 ns) = 5.682 ns; Loc. = LC_X36_Y1_N2; Fanout = 4; COMB Node = 'inst13'
    Info: 3: + IC(3.667 ns) + CELL(2.495 ns) = 11.844 ns; Loc. = PIN_L19; Fanout = 0; PIN Node = 'LED7'
    Info: Total cell delay = 3.877 ns ( 32.73 % )
    Info: Total interconnect delay = 7.967 ns ( 67.27 % )
Info: th for register "eisenbahn_automat:inst1|inst37" (data pin = "DEP_IN0", clock pin = "PLD_CLOCKINPUT") is -0.079 ns
    Info: + Offset between input clock "PLD_CLOCKINPUT" and output clock "altpll0:inst26|altpll:altpll_component|_clk0" is -1.561 ns
    Info: + Longest clock path from clock "altpll0:inst26|altpll:altpll_component|_clk0" to destination register is 7.528 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 10; CLK Node = 'altpll0:inst26|altpll:altpll_component|_clk0'
        Info: 2: + IC(1.429 ns) + CELL(0.736 ns) = 2.165 ns; Loc. = LC_X1_Y18_N5; Fanout = 3; REG Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|safe_q[0]'
        Info: 3: + IC(0.413 ns) + CELL(0.344 ns) = 2.922 ns; Loc. = LC_X1_Y18_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella0~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 2.982 ns; Loc. = LC_X1_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella1~COUT'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 3.042 ns; Loc. = LC_X1_Y18_N7; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella2~COUT'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.102 ns; Loc. = LC_X1_Y18_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella3~COUT'
        Info: 7: + IC(0.000 ns) + CELL(0.219 ns) = 3.321 ns; Loc. = LC_X1_Y18_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella4~COUT'
        Info: 8: + IC(0.000 ns) + CELL(0.110 ns) = 3.431 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|counter_cella9~COUT'
        Info: 9: + IC(0.000 ns) + CELL(0.472 ns) = 3.903 ns; Loc. = LC_X1_Y17_N5; Fanout = 3; COMB Node = 'lpm_counter0:inst27|lpm_counter:lpm_counter_component|cntr_v1b:auto_generated|cout'
        Info: 10: + IC(3.065 ns) + CELL(0.560 ns) = 7.528 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
        Info: Total cell delay = 2.621 ns ( 34.82 % )
        Info: Total interconnect delay = 4.907 ns ( 65.18 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 6.146 ns
        Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_W19; Fanout = 2; PIN Node = 'DEP_IN0'
        Info: 2: + IC(4.418 ns) + CELL(0.213 ns) = 5.772 ns; Loc. = LC_X12_Y1_N7; Fanout = 1; COMB Node = 'eisenbahn_automat:inst1|inst37~97'
        Info: 3: + IC(0.139 ns) + CELL(0.235 ns) = 6.146 ns; Loc. = LC_X12_Y1_N8; Fanout = 9; REG Node = 'eisenbahn_automat:inst1|inst37'
        Info: Total cell delay = 1.589 ns ( 25.85 % )
        Info: Total interconnect delay = 4.557 ns ( 74.15 % )
Info: All timing requirements were met. See Report window for more details.
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jun 29 15:27:57 2006
    Info: Elapsed time: 00:00:02


