Analysis & Synthesis report for Wuerfelzaehler
Thu Jun 22 14:56:16 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Analysis & Synthesis Equations
  9. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jun 22 14:56:16 2006    ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; Wuerfelzaehler                           ;
; Top-level Entity Name       ; Wuerfelzaehler                           ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 87                                       ;
; Total pins                  ; 13                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; DSP block 9-bit elements    ; 0                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1S10F780C6       ;                    ;
; Top-level entity name                                              ; Wuerfelzaehler     ; Wuerfelzaehler     ;
; Family name                                                        ; Stratix            ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Stratix/Stratix GX                       ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto DSP Block Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; -1                 ; -1                 ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Maximum Number of M-RAM Memory Blocks                              ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                 ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                 ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------+
; Wuerfelzaehler.bdf               ; yes             ; User Block Diagram/Schematic File  ; H:/Wuerfelzaehlervorlage/Wuerfelzaehler.bdf  ;
; buttonInterface.vhd              ; yes             ; User VHDL File                     ; H:/Wuerfelzaehlervorlage/buttonInterface.vhd ;
; würfellogik.bdf                  ; yes             ; User Block Diagram/Schematic File  ; H:/Wuerfelzaehlervorlage/würfellogik.bdf     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 87      ;
;     -- Combinational with no register       ; 51      ;
;     -- Register only                        ; 30      ;
;     -- Combinational with a register        ; 6       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 22      ;
;     -- 3 input functions                    ; 2       ;
;     -- 2 input functions                    ; 32      ;
;     -- 1 input functions                    ; 1       ;
;     -- 0 input functions                    ; 0       ;
;         -- Combinational cells for routing  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 57      ;
;     -- arithmetic mode                      ; 30      ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 36      ;
;                                             ;         ;
; Total registers                             ; 36      ;
; Total logic cells in carry chains           ; 31      ;
; I/O pins                                    ; 13      ;
; Maximum fan-out node                        ; reset_n ;
; Maximum fan-out                             ; 36      ;
; Total fan-out                               ; 269     ;
; Average fan-out                             ; 2.69    ;
+---------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                   ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------+
; |Wuerfelzaehler            ; 87 (13)     ; 36           ; 0           ; 0            ; 0       ; 0         ; 0         ; 13   ; 0            ; 51 (13)      ; 30 (0)            ; 6 (0)            ; 31 (0)          ; 0 (0)      ; |Wuerfelzaehler                       ;
;    |buttonInterface:inst9| ; 70 (70)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 38 (38)      ; 30 (30)           ; 2 (2)            ; 31 (31)         ; 0 (0)      ; |Wuerfelzaehler|buttonInterface:inst9 ;
;    |würfellogik:inst|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |Wuerfelzaehler|würfellogik:inst      ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 36    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 36    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/Wuerfelzaehlervorlage/Wuerfelzaehler.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 22 14:56:14 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Wuerfelzaehler -c Wuerfelzaehler
Info: Found 1 design units, including 1 entities, in source file Wuerfelzaehler.bdf
    Info: Found entity 1: Wuerfelzaehler
Info: Found 2 design units, including 1 entities, in source file buttonInterface.vhd
    Info: Found design unit 1: buttonInterface-BI
    Info: Found entity 1: buttonInterface
Info: Found 1 design units, including 1 entities, in source file logik.bdf
    Info: Found entity 1: logik
Info: Found 1 design units, including 1 entities, in source file würfellogik.bdf
    Info: Found entity 1: würfellogik
Info: Elaborating entity "Wuerfelzaehler" for the top level hierarchy
Info: Elaborating entity "buttonInterface" for hierarchy "buttonInterface:inst9"
Info: Elaborating entity "würfellogik" for hierarchy "würfellogik:inst"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "reconf_n" stuck at VCC
Info: Implemented 100 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 9 output pins
    Info: Implemented 87 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jun 22 14:56:16 2006
    Info: Elapsed time: 00:00:03


