Analysis & Synthesis report for DEP-CPU
Mon Jul 17 15:19:58 2006
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |Vorlage|io_interface:inst|display_interface:display_interface_inst|state
  9. State Machine - |Vorlage|io_interface:inst|led_interface:led_interface_inst|mode
 10. State Machine - |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode
 11. State Machine - |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode
 12. User-Specified and Inferred Latches
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (No Restructuring Performed)
 16. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component
 17. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated
 18. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|altsyncram_l1v:fifo_ram
 19. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers
 20. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers|dffpipe_fd9:dffpipe10
 21. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers
 22. Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers|dffpipe_gd9:dffpipe14
 23. Source assignments for io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|altsyncram_vh11:FIFOram
 24. Source assignments for io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component|altsyncram_k431:auto_generated
 25. Source assignments for RAM:inst4|altsyncram:ram_component|altsyncram_fe71:auto_generated
 26. Source assignments for ROM:inst1|altsyncram:rom_component0|altsyncram_4j91:auto_generated
 27. Source assignments for ROM:inst1|altsyncram:rom_component1|altsyncram_5j91:auto_generated
 28. Source assignments for ROM:inst1|altsyncram:rom_component2|altsyncram_6j91:auto_generated
 29. Source assignments for ROM:inst1|altsyncram:rom_component3|altsyncram_7j91:auto_generated
 30. Parameter Settings for User Entity Instance: io_interface:inst
 31. Parameter Settings for User Entity Instance: io_interface:inst|main_pll_configurable:main_pll_configurable_inst
 32. Parameter Settings for User Entity Instance: io_interface:inst|main_pll_configurable:main_pll_configurable_inst|altpll:main_pll_inst
 33. Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst
 34. Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component
 35. Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel
 36. Parameter Settings for User Entity Instance: io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst
 37. Parameter Settings for User Entity Instance: io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component
 38. Parameter Settings for User Entity Instance: io_interface:inst|rom_loader:rom_loader_inst
 39. Parameter Settings for User Entity Instance: DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3|lpm_or:lpm_or_component
 40. Parameter Settings for User Entity Instance: DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|lpm_or8:inst20|lpm_or:lpm_or_component
 41. Parameter Settings for User Entity Instance: DEP-CPU:inst2|lpm_bustri0:8TBUF|lpm_bustri:lpm_bustri_component
 42. Parameter Settings for User Entity Instance: RAM:inst4|altsyncram:ram_component
 43. Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component0
 44. Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component1
 45. Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component2
 46. Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component3
 47. dcfifo Parameter Settings by Entity Instance
 48. scfifo Parameter Settings by Entity Instance
 49. Analysis & Synthesis Equations
 50. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 17 15:19:57 2006         ;
; Quartus II Version          ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name               ; DEP-CPU                                       ;
; Top-level Entity Name       ; Vorlage                                       ;
; Family                      ; Stratix                                       ;
; Total logic elements        ; 1,596                                         ;
; Total pins                  ; 68                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 11,840                                        ;
; DSP block 9-bit elements    ; 0                                             ;
; Total PLLs                  ; 1                                             ;
; Total DLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1S10F780C6       ;                    ;
; Top-level entity name                                              ; Vorlage            ; DEP-CPU            ;
; Family name                                                        ; Stratix            ; Stratix            ;
; Use smart compilation                                              ; On                 ; Off                ;
; Optimization Technique -- Stratix/Stratix GX                       ; Speed              ; Balanced           ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto DSP Block Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; -1                 ; -1                 ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Maximum Number of M-RAM Memory Blocks                              ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                          ;
+------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path   ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                        ;
+------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; Vorlage.bdf                        ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/Vorlage.bdf                                      ;
; ROM.vhd                            ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/ROM.vhd                                          ;
; RAM.vhd                            ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/RAM.vhd                                          ;
; io_interface.vhd                   ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/io_interface.vhd                                 ;
; address_decoder.vhd                ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/address_decoder.vhd                              ;
; release_id.vhd                     ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/release_id.vhd                                   ;
; rom_selector.vhd                   ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/rom_selector.vhd                                 ;
; button_interface.vhd               ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/button_interface.vhd                             ;
; rail_interface.vhd                 ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/rail_interface.vhd                               ;
; DoubleSevenSegmentDecoder.vhd      ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/DoubleSevenSegmentDecoder.vhd                    ;
; seven_segment_interface.vhd        ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/seven_segment_interface.vhd                      ;
; led_interface.vhd                  ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/led_interface.vhd                                ;
; display_interface.vhd              ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/display_interface.vhd                            ;
; fifo.vhd                           ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/fifo.vhd                                         ;
; lifo.vhd                           ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/lifo.vhd                                         ;
; main_pll_configurable.vhd          ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/main_pll_configurable.vhd                        ;
; counters.vhd                       ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/counters.vhd                                     ;
; rom_loader.vhd                     ; yes             ; User VHDL File                     ; H:/dep-cpu_vorlage/rom_loader.vhd                                   ;
; halbaddierer_mtwo.bdf              ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/halbaddierer_mtwo.bdf                            ;
; volladdierer_mtwo.bdf              ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/volladdierer_mtwo.bdf                            ;
; 8bitaddierer_subtrahierer_mtwo.bdf ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/8bitaddierer_subtrahierer_mtwo.bdf               ;
; incrim_mtwo.bdf                    ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/incrim_mtwo.bdf                                  ;
; multiplexer_mtwo.bdf               ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/multiplexer_mtwo.bdf                             ;
; 8bitmultiplexer_mtwo.bdf           ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/8bitmultiplexer_mtwo.bdf                         ;
; registeren_2bit.bdf                ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/registeren_2bit.bdf                              ;
; register_2bit.bdf                  ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/register_2bit.bdf                                ;
; registeren_8bit.bdf                ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/registeren_8bit.bdf                              ;
; registeren_8bit_reset.bdf          ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/registeren_8bit_reset.bdf                        ;
; DEP-CPU.bdf                        ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/DEP-CPU.bdf                                      ;
; decoder.bdf                        ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/decoder.bdf                                      ;
; ALU.bdf                            ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/ALU.bdf                                          ;
; 2bitmultiplexer_mtwo.bdf           ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/2bitmultiplexer_mtwo.bdf                         ;
; ALU_logik.bdf                      ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/ALU_logik.bdf                                    ;
; ALU_arithmetik.bdf                 ; yes             ; User Block Diagram/Schematic File  ; H:/dep-cpu_vorlage/ALU_arithmetik.bdf                               ;
; altpll.tdf                         ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/altpll.tdf              ;
; aglobal51.inc                      ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc           ;
; stratix_pll.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/stratix_pll.inc         ;
; stratixii_pll.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/stratixii_pll.inc       ;
; cycloneii_pll.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/cycloneii_pll.inc       ;
; dcfifo.tdf                         ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/dcfifo.tdf              ;
; lpm_counter.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_counter.inc         ;
; lpm_add_sub.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.inc         ;
; altdpram.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altdpram.inc            ;
; a_graycounter.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_graycounter.inc       ;
; a_fefifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_fefifo.inc            ;
; a_gray2bin.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_gray2bin.inc          ;
; dffpipe.inc                        ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/dffpipe.inc             ;
; alt_sync_fifo.inc                  ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_sync_fifo.inc       ;
; lpm_compare.inc                    ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_compare.inc         ;
; altsyncram_fifo.inc                ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altsyncram_fifo.inc     ;
; db/dcfifo_4941.tdf                 ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/dcfifo_4941.tdf                               ;
; db/a_gray2bin_k5b.tdf              ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/a_gray2bin_k5b.tdf                            ;
; db/a_graycounter_i16.tdf           ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/a_graycounter_i16.tdf                         ;
; db/a_graycounter_j16.tdf           ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/a_graycounter_j16.tdf                         ;
; db/altsyncram_l1v.tdf              ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_l1v.tdf                            ;
; db/alt_synch_pipe_lc8.tdf          ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/alt_synch_pipe_lc8.tdf                        ;
; db/dffpipe_fd9.tdf                 ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/dffpipe_fd9.tdf                               ;
; db/alt_synch_pipe_mc8.tdf          ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/alt_synch_pipe_mc8.tdf                        ;
; db/dffpipe_gd9.tdf                 ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/dffpipe_gd9.tdf                               ;
; db/add_sub_avb.tdf                 ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/add_sub_avb.tdf                               ;
; db/cntr_uv7.tdf                    ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/cntr_uv7.tdf                                  ;
; scfifo.tdf                         ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/scfifo.tdf              ;
; a_regfifo.inc                      ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_regfifo.inc           ;
; a_dpfifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_dpfifo.inc            ;
; a_i2fifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_i2fifo.inc            ;
; a_fffifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_fffifo.inc            ;
; a_f2fifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_f2fifo.inc            ;
; a_f2fifo.tdf                       ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/a_f2fifo.tdf            ;
; lpm_ff.inc                         ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_ff.inc              ;
; a_mxfifo.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_mxfifo.inc            ;
; lpm_counter.tdf                    ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                   ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.inc          ;
; cmpconst.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/cmpconst.inc            ;
; dffeea.inc                         ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc              ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc            ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc              ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc            ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_g1b.tdf                    ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/cntr_g1b.tdf                                  ;
; lpm_ff.tdf                         ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf              ;
; db/scfifo_rbn.tdf                  ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/scfifo_rbn.tdf                                ;
; db/a_dpfifo_a3n.tdf                ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/a_dpfifo_a3n.tdf                              ;
; db/altsyncram_vh11.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_vh11.tdf                           ;
; db/cntr_se8.tdf                    ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/cntr_se8.tdf                                  ;
; db/cntr_bd7.tdf                    ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/cntr_bd7.tdf                                  ;
; db/cntr_te8.tdf                    ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/cntr_te8.tdf                                  ;
; altsyncram.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf          ;
; stratix_ram_block.inc              ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc   ;
; lpm_mux.inc                        ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/lpm_mux.inc             ;
; altsyncram.inc                     ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altsyncram.inc          ;
; a_rdenreg.inc                      ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc           ;
; altrom.inc                         ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altrom.inc              ;
; altram.inc                         ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altram.inc              ;
; altqpram.inc                       ; yes             ; Other                              ; c:/altera/quartus51/libraries/megafunctions/altqpram.inc            ;
; db/altsyncram_k431.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_k431.tdf                           ;
; 8bitOr.bdf                         ; yes             ; Other                              ; H:/dep-cpu_vorlage/8bitOr.bdf                                       ;
; 8bitXOr.bdf                        ; yes             ; Other                              ; H:/dep-cpu_vorlage/8bitXOr.bdf                                      ;
; 8bitAnd.bdf                        ; yes             ; Other                              ; H:/dep-cpu_vorlage/8bitAnd.bdf                                      ;
; lpm_or8.vhd                        ; yes             ; Other                              ; H:/dep-cpu_vorlage/lpm_or8.vhd                                      ;
; lpm_or.tdf                         ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_or.tdf              ;
; lpm_bustri0.vhd                    ; yes             ; Other                              ; H:/dep-cpu_vorlage/lpm_bustri0.vhd                                  ;
; lpm_bustri.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf          ;
; db/altsyncram_fe71.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_fe71.tdf                           ;
; db/altsyncram_4j91.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_4j91.tdf                           ;
; db/altsyncram_5j91.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_5j91.tdf                           ;
; db/altsyncram_6j91.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_6j91.tdf                           ;
; db/altsyncram_7j91.tdf             ; yes             ; Auto-Generated Megafunction        ; H:/dep-cpu_vorlage/db/altsyncram_7j91.tdf                           ;
+------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                            ;
+---------------------------------------------+----------------------------------------------------------+
; Resource                                    ; Usage                                                    ;
+---------------------------------------------+----------------------------------------------------------+
; Total logic elements                        ; 1596                                                     ;
;     -- Combinational with no register       ; 987                                                      ;
;     -- Register only                        ; 245                                                      ;
;     -- Combinational with a register        ; 364                                                      ;
;                                             ;                                                          ;
; Logic element usage by number of LUT inputs ;                                                          ;
;     -- 4 input functions                    ; 691                                                      ;
;     -- 3 input functions                    ; 341                                                      ;
;     -- 2 input functions                    ; 307                                                      ;
;     -- 1 input functions                    ; 11                                                       ;
;     -- 0 input functions                    ; 1                                                        ;
;         -- Combinational cells for routing  ; 0                                                        ;
;                                             ;                                                          ;
; Logic elements by mode                      ;                                                          ;
;     -- normal mode                          ; 1240                                                     ;
;     -- arithmetic mode                      ; 356                                                      ;
;     -- qfbk mode                            ; 0                                                        ;
;     -- register cascade mode                ; 0                                                        ;
;     -- synchronous clear/load mode          ; 81                                                       ;
;     -- asynchronous clear/load mode         ; 515                                                      ;
;                                             ;                                                          ;
; Total registers                             ; 609                                                      ;
; Total logic cells in carry chains           ; 376                                                      ;
; I/O pins                                    ; 68                                                       ;
; Total memory bits                           ; 11840                                                    ;
; Total PLLs                                  ; 1                                                        ;
; Maximum fan-out node                        ; io_interface:inst|rom_loader:rom_loader_inst|reset_n_out ;
; Maximum fan-out                             ; 411                                                      ;
; Total fan-out                               ; 7248                                                     ;
; Average fan-out                             ; 4.19                                                     ;
+---------------------------------------------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                   ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                                                                                                                  ;
+--------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |Vorlage                                                     ; 1596 (1)    ; 609          ; 11840       ; 0            ; 0       ; 0         ; 0         ; 68   ; 0            ; 987 (1)      ; 245 (0)           ; 364 (0)          ; 376 (0)         ; 0 (0)      ; |Vorlage                                                                                                                                                                             ;
;    |DEP-CPU:inst2|                                           ; 107 (0)     ; 36           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 71 (0)       ; 18 (0)            ; 18 (0)           ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2                                                                                                                                                               ;
;       |8bitmultiplexer_mtwo:MuxAB|                           ; 9 (9)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|8bitmultiplexer_mtwo:MuxAB                                                                                                                                    ;
;       |ALU:ALU|                                              ; 34 (0)      ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 34 (0)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU                                                                                                                                                       ;
;          |2bitmultiplexer_mtwo:inst3|                        ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|2bitmultiplexer_mtwo:inst3                                                                                                                            ;
;          |ALU_arithmetik:inst1|                              ; 22 (4)      ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 22 (4)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1                                                                                                                                  ;
;             |8bitaddierer_subtrahierer_mtwo:inst17|          ; 15 (0)      ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 15 (0)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17                                                                                            ;
;                |volladdierer_mtwo:inst1|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst1                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst1|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst2|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst2                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst2|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst3|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst3                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst3|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst4|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst4                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst4|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst5|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst5                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst5|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst7|                     ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst7                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst7|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst8|                     ; 1 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst8                                                                    ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst8|halbaddierer_mtwo:inst                                             ;
;                |volladdierer_mtwo:inst|                      ; 2 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst                                                                     ;
;                   |halbaddierer_mtwo:inst|                   ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst|halbaddierer_mtwo:inst                                              ;
;             |lpm_or8:inst20|                                 ; 3 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|lpm_or8:inst20                                                                                                                   ;
;                |lpm_or:lpm_or_component|                     ; 3 (3)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|lpm_or8:inst20|lpm_or:lpm_or_component                                                                                           ;
;          |ALU_logik:inst|                                    ; 11 (0)      ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 11 (0)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_logik:inst                                                                                                                                        ;
;             |8bitmultiplexer_mtwo:inst2|                     ; 8 (8)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|8bitmultiplexer_mtwo:inst2                                                                                                             ;
;             |lpm_or8:inst3|                                  ; 3 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3                                                                                                                          ;
;                |lpm_or:lpm_or_component|                     ; 3 (3)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3|lpm_or:lpm_or_component                                                                                                  ;
;       |decoder:Decoder|                                      ; 14 (14)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|decoder:Decoder                                                                                                                                               ;
;       |incrim_mtwo:inst|                                     ; 5 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst                                                                                                                                              ;
;          |halbaddierer_mtwo:inst1|                           ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst|halbaddierer_mtwo:inst1                                                                                                                      ;
;          |halbaddierer_mtwo:inst2|                           ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst|halbaddierer_mtwo:inst2                                                                                                                      ;
;          |halbaddierer_mtwo:inst3|                           ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst|halbaddierer_mtwo:inst3                                                                                                                      ;
;          |halbaddierer_mtwo:inst4|                           ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst|halbaddierer_mtwo:inst4                                                                                                                      ;
;          |halbaddierer_mtwo:inst|                            ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|incrim_mtwo:inst|halbaddierer_mtwo:inst                                                                                                                       ;
;       |lpm_bustri0:8TBUF|                                    ; 8 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|lpm_bustri0:8TBUF                                                                                                                                             ;
;          |lpm_bustri:lpm_bustri_component|                   ; 8 (8)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|lpm_bustri0:8TBUF|lpm_bustri:lpm_bustri_component                                                                                                             ;
;       |register_2bit:MSR|                                    ; 2 (2)       ; 2            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|register_2bit:MSR                                                                                                                                             ;
;       |registeren_2bit:CCR|                                  ; 2 (2)       ; 2            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|registeren_2bit:CCR                                                                                                                                           ;
;       |registeren_8bit:ACCR|                                 ; 8 (8)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|registeren_8bit:ACCR                                                                                                                                          ;
;       |registeren_8bit:IWR|                                  ; 8 (8)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|registeren_8bit:IWR                                                                                                                                           ;
;       |registeren_8bit:OPR|                                  ; 8 (8)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|registeren_8bit:OPR                                                                                                                                           ;
;       |registeren_8bit_reset:PCR|                            ; 9 (9)       ; 8            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 7 (7)            ; 0 (0)           ; 0 (0)      ; |Vorlage|DEP-CPU:inst2|registeren_8bit_reset:PCR                                                                                                                                     ;
;    |RAM:inst4|                                               ; 9 (9)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|RAM:inst4                                                                                                                                                                   ;
;       |altsyncram:ram_component|                             ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|RAM:inst4|altsyncram:ram_component                                                                                                                                          ;
;          |altsyncram_fe71:auto_generated|                    ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|RAM:inst4|altsyncram:ram_component|altsyncram_fe71:auto_generated                                                                                                           ;
;    |ROM:inst1|                                               ; 63 (63)     ; 0            ; 8192        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 63 (63)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1                                                                                                                                                                   ;
;       |altsyncram:rom_component0|                            ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component0                                                                                                                                         ;
;          |altsyncram_4j91:auto_generated|                    ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component0|altsyncram_4j91:auto_generated                                                                                                          ;
;       |altsyncram:rom_component1|                            ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component1                                                                                                                                         ;
;          |altsyncram_5j91:auto_generated|                    ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component1|altsyncram_5j91:auto_generated                                                                                                          ;
;       |altsyncram:rom_component2|                            ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component2                                                                                                                                         ;
;          |altsyncram_6j91:auto_generated|                    ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component2|altsyncram_6j91:auto_generated                                                                                                          ;
;       |altsyncram:rom_component3|                            ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component3                                                                                                                                         ;
;          |altsyncram_7j91:auto_generated|                    ; 0 (0)       ; 0            ; 2048        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|ROM:inst1|altsyncram:rom_component3|altsyncram_7j91:auto_generated                                                                                                          ;
;    |io_interface:inst|                                       ; 1416 (42)   ; 573          ; 1600        ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 843 (42)     ; 227 (0)           ; 346 (0)          ; 376 (0)         ; 0 (0)      ; |Vorlage|io_interface:inst                                                                                                                                                           ;
;       |address_decoder:address_decoder_inst|                 ; 7 (7)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|address_decoder:address_decoder_inst                                                                                                                      ;
;       |button_interface:button_interface_inst|               ; 7 (7)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|button_interface:button_interface_inst                                                                                                                    ;
;       |counters:counters_inst|                               ; 389 (389)   ; 156          ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 233 (233)    ; 32 (32)           ; 124 (124)        ; 124 (124)       ; 0 (0)      ; |Vorlage|io_interface:inst|counters:counters_inst                                                                                                                                    ;
;       |display_interface:display_interface_inst|             ; 339 (212)   ; 182          ; 576         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 157 (144)    ; 103 (49)          ; 79 (19)          ; 95 (62)         ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst                                                                                                                  ;
;          |dcfifo:dcfifo_component|                           ; 127 (0)     ; 114          ; 576         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (0)       ; 54 (0)            ; 60 (0)           ; 33 (0)          ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component                                                                                          ;
;             |dcfifo_4941:auto_generated|                     ; 127 (29)    ; 114          ; 576         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (8)       ; 54 (9)            ; 60 (12)          ; 33 (6)          ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated                                                               ;
;                |a_gray2bin_k5b:write_side_gray_converter|    ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_gray2bin_k5b:write_side_gray_converter                      ;
;                |a_graycounter_i16:rdptr_g|                   ; 7 (7)       ; 7            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 7 (7)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_graycounter_i16:rdptr_g                                     ;
;                |a_graycounter_i16:wrptr_g|                   ; 7 (7)       ; 7            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 7 (7)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_graycounter_i16:wrptr_g                                     ;
;                |a_graycounter_j16:read_counter_for_write|    ; 7 (7)       ; 7            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 7 (7)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_graycounter_j16:read_counter_for_write                      ;
;                |alt_synch_pipe_lc8:read_sync_registers|      ; 18 (0)      ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers                        ;
;                   |dffpipe_fd9:dffpipe10|                    ; 18 (18)     ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers|dffpipe_fd9:dffpipe10  ;
;                |alt_synch_pipe_mc8:write_sync_registers|     ; 18 (0)      ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers                       ;
;                   |dffpipe_gd9:dffpipe14|                    ; 18 (18)     ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers|dffpipe_gd9:dffpipe14 ;
;                |altsyncram_l1v:fifo_ram|                     ; 0 (0)       ; 0            ; 576         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|altsyncram_l1v:fifo_ram                                       ;
;                |cntr_uv7:wrptr_b|                            ; 6 (6)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|cntr_uv7:wrptr_b                                              ;
;                |scfifo:output_channel|                       ; 34 (0)      ; 30           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 4 (0)        ; 9 (0)             ; 21 (0)           ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel                                         ;
;                   |a_f2fifo:subfifo|                         ; 34 (6)      ; 30           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 4 (4)        ; 9 (0)             ; 21 (2)           ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo                        ;
;                      |lpm_ff:$00002|                         ; 9 (9)       ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00002          ;
;                      |lpm_ff:$00004|                         ; 9 (9)       ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00004          ;
;                      |lpm_ff:$00006|                         ; 9 (9)       ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00006          ;
;                      |lpm_ff:$00010|                         ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00010          ;
;       |fifo:fifo_inst|                                       ; 76 (13)     ; 31           ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 45 (13)      ; 3 (0)             ; 28 (0)           ; 17 (0)          ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst                                                                                                                                            ;
;          |scfifo:fifo_inst|                                  ; 63 (0)      ; 31           ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 32 (0)       ; 3 (0)             ; 28 (0)           ; 17 (0)          ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst                                                                                                                           ;
;             |scfifo_rbn:auto_generated|                      ; 63 (0)      ; 31           ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 32 (0)       ; 3 (0)             ; 28 (0)           ; 17 (0)          ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated                                                                                                 ;
;                |a_dpfifo_a3n:dpfifo|                         ; 63 (45)     ; 31           ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 32 (31)      ; 3 (3)             ; 28 (11)          ; 17 (0)          ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo                                                                             ;
;                   |altsyncram_vh11:FIFOram|                  ; 0 (0)       ; 0            ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|altsyncram_vh11:FIFOram                                                     ;
;                   |cntr_bd7:usedw_counter|                   ; 7 (7)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_bd7:usedw_counter                                                      ;
;                   |cntr_se8:rd_ptr_msb|                      ; 5 (5)       ; 5            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 5 (5)           ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_se8:rd_ptr_msb                                                         ;
;                   |cntr_te8:wr_ptr|                          ; 6 (6)       ; 6            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; 0 (0)      ; |Vorlage|io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_te8:wr_ptr                                                             ;
;       |led_interface:led_interface_inst|                     ; 32 (32)     ; 11           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 21 (21)      ; 8 (8)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|led_interface:led_interface_inst                                                                                                                          ;
;       |lifo:lifo_inst|                                       ; 50 (50)     ; 6            ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 44 (44)      ; 0 (0)             ; 6 (6)            ; 6 (6)           ; 0 (0)      ; |Vorlage|io_interface:inst|lifo:lifo_inst                                                                                                                                            ;
;          |altsyncram:altsyncram_component|                   ; 0 (0)       ; 0            ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component                                                                                                            ;
;             |altsyncram_k431:auto_generated|                 ; 0 (0)       ; 0            ; 512         ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component|altsyncram_k431:auto_generated                                                                             ;
;       |main_pll_configurable:main_pll_configurable_inst|     ; 115 (115)   ; 38           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 77 (77)      ; 31 (31)           ; 7 (7)            ; 31 (31)         ; 0 (0)      ; |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst                                                                                                          ;
;          |altpll:main_pll_inst|                              ; 0 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|altpll:main_pll_inst                                                                                     ;
;       |rail_interface:rail_interface_inst|                   ; 11 (11)     ; 5            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 6 (6)        ; 3 (3)             ; 2 (2)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|rail_interface:rail_interface_inst                                                                                                                        ;
;       |release_id:release_id_inst|                           ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|release_id:release_id_inst                                                                                                                                ;
;       |rom_loader:rom_loader_inst|                           ; 236 (236)   ; 115          ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 121 (121)    ; 29 (29)           ; 86 (86)          ; 103 (103)       ; 0 (0)      ; |Vorlage|io_interface:inst|rom_loader:rom_loader_inst                                                                                                                                ;
;       |rom_selector:rom_selector_inst|                       ; 7 (7)       ; 2            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 5 (5)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|rom_selector:rom_selector_inst                                                                                                                            ;
;       |seven_segment_interface:seven_segment_interface_inst| ; 104 (90)    ; 23           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 81 (67)      ; 16 (16)           ; 7 (7)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst                                                                                                      ;
;          |DoubleSevenSegmentDecoder:double_ss_dec|           ; 14 (14)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|DoubleSevenSegmentDecoder:double_ss_dec                                                              ;
+--------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+---------------+
; Name                                                                                                                                             ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+---------------+
; RAM:inst4|altsyncram:ram_component|altsyncram_fe71:auto_generated|ALTSYNCRAM                                                                     ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048 ; INIT/ram.mif  ;
; ROM:inst1|altsyncram:rom_component0|altsyncram_4j91:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048 ; INIT/rom0.mif ;
; ROM:inst1|altsyncram:rom_component1|altsyncram_5j91:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048 ; INIT/rom1.mif ;
; ROM:inst1|altsyncram:rom_component2|altsyncram_6j91:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048 ; INIT/rom2.mif ;
; ROM:inst1|altsyncram:rom_component3|altsyncram_7j91:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048 ; INIT/rom3.mif ;
; io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|altsyncram_l1v:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 9            ; 64           ; 9            ; 576  ; None          ;
; io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|altsyncram_vh11:FIFOram|ALTSYNCRAM               ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512  ; None          ;
; io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component|altsyncram_k431:auto_generated|ALTSYNCRAM                                       ; AUTO ; Single Port      ; 64           ; 8            ; --           ; --           ; 512  ; None          ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Vorlage|io_interface:inst|display_interface:display_interface_inst|state                                      ;
+-----------------------+----------+-----------------------+-----------------------+-----------------------+---------------------+
; Name                  ; state.ok ; state.after_3rd_reset ; state.after_2nd_reset ; state.after_1st_reset ; state.wait_power_up ;
+-----------------------+----------+-----------------------+-----------------------+-----------------------+---------------------+
; state.wait_power_up   ; 0        ; 0                     ; 0                     ; 0                     ; 0                   ;
; state.after_1st_reset ; 0        ; 0                     ; 0                     ; 1                     ; 1                   ;
; state.after_2nd_reset ; 0        ; 0                     ; 1                     ; 0                     ; 1                   ;
; state.after_3rd_reset ; 0        ; 1                     ; 0                     ; 0                     ; 1                   ;
; state.ok              ; 1        ; 0                     ; 0                     ; 0                     ; 1                   ;
+-----------------------+----------+-----------------------+-----------------------+-----------------------+---------------------+


+----------------------------------------------------------------------------------------------------------------+
; State Machine - |Vorlage|io_interface:inst|led_interface:led_interface_inst|mode                               ;
+-----------------------+-------------------+-----------------------+--------------------+-----------------------+
; Name                  ; mode.show_nothing ; mode.show_custom_data ; mode.show_data_bus ; mode.show_address_bus ;
+-----------------------+-------------------+-----------------------+--------------------+-----------------------+
; mode.show_address_bus ; 0                 ; 0                     ; 0                  ; 0                     ;
; mode.show_data_bus    ; 0                 ; 0                     ; 1                  ; 1                     ;
; mode.show_custom_data ; 0                 ; 1                     ; 0                  ; 1                     ;
; mode.show_nothing     ; 1                 ; 0                     ; 0                  ; 1                     ;
+-----------------------+-------------------+-----------------------+--------------------+-----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode                                                                                                                                     ;
+---------------------------------+-------------------+---------------------------------+--------------------------------+---------------------+-----------------------+----------------------+-----------------------+--------------------+
; Name                            ; mode.show_nothing ; mode.show_custom_segments_right ; mode.show_custom_segments_left ; mode.show_rail_info ; mode.show_ram_monitor ; mode.show_custom_hex ; mode.show_address_bus ; mode.show_data_bus ;
+---------------------------------+-------------------+---------------------------------+--------------------------------+---------------------+-----------------------+----------------------+-----------------------+--------------------+
; mode.show_data_bus              ; 0                 ; 0                               ; 0                              ; 0                   ; 0                     ; 0                    ; 0                     ; 0                  ;
; mode.show_address_bus           ; 0                 ; 0                               ; 0                              ; 0                   ; 0                     ; 0                    ; 1                     ; 1                  ;
; mode.show_custom_hex            ; 0                 ; 0                               ; 0                              ; 0                   ; 0                     ; 1                    ; 0                     ; 1                  ;
; mode.show_ram_monitor           ; 0                 ; 0                               ; 0                              ; 0                   ; 1                     ; 0                    ; 0                     ; 1                  ;
; mode.show_rail_info             ; 0                 ; 0                               ; 0                              ; 1                   ; 0                     ; 0                    ; 0                     ; 1                  ;
; mode.show_custom_segments_left  ; 0                 ; 0                               ; 1                              ; 0                   ; 0                     ; 0                    ; 0                     ; 1                  ;
; mode.show_custom_segments_right ; 0                 ; 1                               ; 0                              ; 0                   ; 0                     ; 0                    ; 0                     ; 1                  ;
; mode.show_nothing               ; 1                 ; 0                               ; 0                              ; 0                   ; 0                     ; 0                    ; 0                     ; 1                  ;
+---------------------------------+-------------------+---------------------------------+--------------------------------+---------------------+-----------------------+----------------------+-----------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode                                     ;
+-------------------------------+-------------------------------+--------------------------+--------------------------+---------------------------+
; Name                          ; speed_step_mode.external_once ; speed_step_mode.external ; speed_step_mode.software ; speed_step_mode.parameter ;
+-------------------------------+-------------------------------+--------------------------+--------------------------+---------------------------+
; speed_step_mode.parameter     ; 0                             ; 0                        ; 0                        ; 0                         ;
; speed_step_mode.software      ; 0                             ; 0                        ; 1                        ; 1                         ;
; speed_step_mode.external      ; 0                             ; 1                        ; 0                        ; 1                         ;
; speed_step_mode.external_once ; 1                             ; 0                        ; 0                        ; 1                         ;
+-------------------------------+-------------------------------+--------------------------+--------------------------+---------------------------+


+-------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                     ;
+--------------------------------------------------------------------+----+
; Latch Name                                                         ;    ;
+--------------------------------------------------------------------+----+
; io_interface:inst|counters:counters_inst|data[7]$latch             ;    ;
; io_interface:inst|counters:counters_inst|data_891                  ;    ;
; io_interface:inst|counters:counters_inst|data[6]$latch             ;    ;
; io_interface:inst|counters:counters_inst|data[5]$latch             ;    ;
; io_interface:inst|counters:counters_inst|data[4]$latch             ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data[4]$latch ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data_85       ;    ;
; io_interface:inst|counters:counters_inst|data[3]$latch             ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data[3]$latch ;    ;
; io_interface:inst|counters:counters_inst|data[2]$latch             ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data[2]$latch ;    ;
; io_interface:inst|counters:counters_inst|data[1]$latch             ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data[1]$latch ;    ;
; io_interface:inst|counters:counters_inst|data[0]$latch             ;    ;
; io_interface:inst|rail_interface:rail_interface_inst|data[0]$latch ;    ;
; Number of user-specified and inferred latches                      ; 15 ;
+--------------------------------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 609   ;
; Number of registers using Synchronous Clear  ; 58    ;
; Number of registers using Synchronous Load   ; 23    ;
; Number of registers using Asynchronous Clear ; 515   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 173   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------+
; Inverted Register Statistics                                         ;
+------------------------------------------------------------+---------+
; Inverted Register                                          ; Fan out ;
+------------------------------------------------------------+---------+
; io_interface:inst|rom_loader:rom_loader_inst|v_reset_n_out ; 4       ;
; io_interface:inst|rom_loader:rom_loader_inst|wr_en_n       ; 6       ;
; Total number of inverted registers = 2                     ;         ;
+------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
; 4:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|counter[10]                ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |Vorlage|io_interface:inst|lifo:lifo_inst|write_address[1]                                     ;
; 4:1                ; 28 bits   ; 56 LEs        ; 56 LEs               ; 0 LEs                  ; Yes        ; |Vorlage|io_interface:inst|rom_loader:rom_loader_inst|state[11]                                ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |Vorlage|io_interface:inst|rom_loader:rom_loader_inst|state[3]                                 ;
; 4:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |Vorlage|io_interface:inst|counters:counters_inst|counter[3][28]                               ;
; 4:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |Vorlage|io_interface:inst|counters:counters_inst|counter[2][0]                                ;
; 4:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |Vorlage|io_interface:inst|counters:counters_inst|counter[1][27]                               ;
; 4:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |Vorlage|io_interface:inst|counters:counters_inst|counter[0][6]                                ;
; 5:1                ; 31 bits   ; 93 LEs        ; 31 LEs               ; 62 LEs                 ; Yes        ; |Vorlage|io_interface:inst|rom_loader:rom_loader_inst|timeout[15]                              ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|v_speed_step[1]    ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |Vorlage|DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|8bitmultiplexer_mtwo:inst2|inst39                ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |Vorlage|io_interface:inst|led_interface:led_interface_inst|led[7]                             ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |Vorlage|ROM:inst1|data~17                                                                     ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; No         ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|s_bin_data[2]  ;
; 5:1                ; 4 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|dsseg[9]       ;
; 5:1                ; 5 bits    ; 15 LEs        ; 15 LEs               ; 0 LEs                  ; No         ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|state~15                   ;
; 6:1                ; 10 bits   ; 40 LEs        ; 30 LEs               ; 10 LEs                 ; No         ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|dsseg[4]       ;
; 6:1                ; 4 bits    ; 16 LEs        ; 12 LEs               ; 4 LEs                  ; No         ; |Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode~19 ;
; 9:1                ; 9 bits    ; 54 LEs        ; 54 LEs               ; 0 LEs                  ; No         ; |Vorlage|io_interface:inst|display_interface:display_interface_inst|display_rd_not_wr          ;
; 257:1              ; 4 bits    ; 684 LEs       ; 12 LEs               ; 672 LEs                ; No         ; |Vorlage|io_interface:inst|led_interface:led_interface_inst|mode~1                             ;
; 257:1              ; 8 bits    ; 1368 LEs      ; 48 LEs               ; 1320 LEs               ; No         ; |Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode~0         ;
; 16:1               ; 7 bits    ; 70 LEs        ; 70 LEs               ; 0 LEs                  ; No         ; |Vorlage|io_interface:inst|counters:counters_inst|data~54                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------------------------------------------------+
; Assignment                      ; Value ; from ; to                                                       ;
+---------------------------------+-------+------+----------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
+---------------------------------+-------+------+----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated    ;
+---------------------------------+-------+------------------------------------------------------+----------------------------------------+
; Assignment                      ; Value ; from                                                 ; to                                     ;
+---------------------------------+-------+------------------------------------------------------+----------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -                                                    ; -                                      ;
; SUPPRESS_DA_RULE_INTERNAL       ; d102  ; -                                                    ; -                                      ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -                                                    ; -                                      ;
; CUT                             ; ON    ; read_counter_for_write|power_modified_counter_values ; write_sync_registers|dffpipe14|dffe15a ;
; CUT                             ; ON    ; delayed_wrptr_g                                      ; read_sync_registers|dffpipe10|dffe11a  ;
+---------------------------------+-------+------------------------------------------------------+----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|altsyncram_l1v:fifo_ram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers ;
+-----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; from ; to                                                                                                                                   ;
+-----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                                                    ;
+-----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers|dffpipe_fd9:dffpipe10 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; from ; to                                                                                                                                               ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers ;
+-----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; from ; to                                                                                                                                    ;
+-----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                                                     ;
+-----------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers|dffpipe_gd9:dffpipe14 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; from ; to                                                                                                                                                ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|altsyncram_vh11:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                               ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component|altsyncram_k431:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Source assignments for RAM:inst4|altsyncram:ram_component|altsyncram_fe71:auto_generated ;
+---------------------------------+--------------------+------+----------------------------+
; Assignment                      ; Value              ; from ; to                         ;
+---------------------------------+--------------------+------+----------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                          ;
+---------------------------------+--------------------+------+----------------------------+


+-------------------------------------------------------------------------------------------+
; Source assignments for ROM:inst1|altsyncram:rom_component0|altsyncram_4j91:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------+
; Assignment                      ; Value              ; from ; to                          ;
+---------------------------------+--------------------+------+-----------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                           ;
+---------------------------------+--------------------+------+-----------------------------+


+-------------------------------------------------------------------------------------------+
; Source assignments for ROM:inst1|altsyncram:rom_component1|altsyncram_5j91:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------+
; Assignment                      ; Value              ; from ; to                          ;
+---------------------------------+--------------------+------+-----------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                           ;
+---------------------------------+--------------------+------+-----------------------------+


+-------------------------------------------------------------------------------------------+
; Source assignments for ROM:inst1|altsyncram:rom_component2|altsyncram_6j91:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------+
; Assignment                      ; Value              ; from ; to                          ;
+---------------------------------+--------------------+------+-----------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                           ;
+---------------------------------+--------------------+------+-----------------------------+


+-------------------------------------------------------------------------------------------+
; Source assignments for ROM:inst1|altsyncram:rom_component3|altsyncram_7j91:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------+
; Assignment                      ; Value              ; from ; to                          ;
+---------------------------------+--------------------+------+-----------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                           ;
+---------------------------------+--------------------+------+-----------------------------+


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; speed_step     ; 0     ; Untyped                               ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|main_pll_configurable:main_pll_configurable_inst ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; f_clk_mult     ; 3     ; Integer                                                                                ;
; f_clk_div      ; 5     ; Integer                                                                                ;
; speed_step     ; 0     ; Integer                                                                                ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|main_pll_configurable:main_pll_configurable_inst|altpll:main_pll_inst ;
+-------------------------------+-------------------+----------------------------------------------------------------------------------+
; Parameter Name                ; Value             ; Type                                                                             ;
+-------------------------------+-------------------+----------------------------------------------------------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                                                                          ;
; PLL_TYPE                      ; AUTO              ; Untyped                                                                          ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                                                          ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                                                          ;
; SCAN_CHAIN                    ; LONG              ; Untyped                                                                          ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                                                          ;
; INCLK0_INPUT_FREQUENCY        ; 20000             ; Integer                                                                          ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                                                          ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                                                          ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                                                          ;
; LOCK_HIGH                     ; 1                 ; Untyped                                                                          ;
; LOCK_LOW                      ; 1                 ; Untyped                                                                          ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                                                          ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                                                          ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                                                          ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                                                          ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                                                          ;
; SKIP_VCO                      ; OFF               ; Untyped                                                                          ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                                                          ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                                                          ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                                                          ;
; BANDWIDTH                     ; 0                 ; Untyped                                                                          ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                                                          ;
; SPREAD_FREQUENCY              ; 0                 ; Integer                                                                          ;
; DOWN_SPREAD                   ; 0                 ; Untyped                                                                          ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                                                          ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                                                          ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                                                          ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                                                          ;
; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                                                          ;
; CLK1_MULTIPLY_BY              ; 1                 ; Untyped                                                                          ;
; CLK0_MULTIPLY_BY              ; 3                 ; Integer                                                                          ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                                                          ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                                                          ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                                                          ;
; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                                                          ;
; CLK1_DIVIDE_BY                ; 1                 ; Untyped                                                                          ;
; CLK0_DIVIDE_BY                ; 5                 ; Integer                                                                          ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                                                          ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                                                                          ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                                                          ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                                                          ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                                                          ;
; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                                                          ;
; CLK1_DUTY_CYCLE               ; 50                ; Untyped                                                                          ;
; CLK0_DUTY_CYCLE               ; 50                ; Integer                                                                          ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                                                          ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                                                          ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                                                          ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                                                          ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                                                          ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                                                          ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                                                          ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                                                          ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                                                          ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                                                          ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                                                          ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                                                          ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                                                          ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                                                          ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                                                          ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                                                          ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                                                          ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                                                          ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                                                          ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                                                          ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                                                          ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                                                          ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                                                          ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                                                          ;
; VCO_MIN                       ; 0                 ; Untyped                                                                          ;
; VCO_MAX                       ; 0                 ; Untyped                                                                          ;
; VCO_CENTER                    ; 0                 ; Untyped                                                                          ;
; PFD_MIN                       ; 0                 ; Untyped                                                                          ;
; PFD_MAX                       ; 0                 ; Untyped                                                                          ;
; M_INITIAL                     ; 0                 ; Untyped                                                                          ;
; M                             ; 0                 ; Untyped                                                                          ;
; N                             ; 1                 ; Untyped                                                                          ;
; M2                            ; 1                 ; Untyped                                                                          ;
; N2                            ; 1                 ; Untyped                                                                          ;
; SS                            ; 1                 ; Untyped                                                                          ;
; C0_HIGH                       ; 0                 ; Untyped                                                                          ;
; C1_HIGH                       ; 0                 ; Untyped                                                                          ;
; C2_HIGH                       ; 0                 ; Untyped                                                                          ;
; C3_HIGH                       ; 0                 ; Untyped                                                                          ;
; C4_HIGH                       ; 0                 ; Untyped                                                                          ;
; C5_HIGH                       ; 0                 ; Untyped                                                                          ;
; C0_LOW                        ; 0                 ; Untyped                                                                          ;
; C1_LOW                        ; 0                 ; Untyped                                                                          ;
; C2_LOW                        ; 0                 ; Untyped                                                                          ;
; C3_LOW                        ; 0                 ; Untyped                                                                          ;
; C4_LOW                        ; 0                 ; Untyped                                                                          ;
; C5_LOW                        ; 0                 ; Untyped                                                                          ;
; C0_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C1_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C2_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C3_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C4_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C5_INITIAL                    ; 0                 ; Untyped                                                                          ;
; C0_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C1_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C2_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C3_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C4_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C5_MODE                       ; BYPASS            ; Untyped                                                                          ;
; C0_PH                         ; 0                 ; Untyped                                                                          ;
; C1_PH                         ; 0                 ; Untyped                                                                          ;
; C2_PH                         ; 0                 ; Untyped                                                                          ;
; C3_PH                         ; 0                 ; Untyped                                                                          ;
; C4_PH                         ; 0                 ; Untyped                                                                          ;
; C5_PH                         ; 0                 ; Untyped                                                                          ;
; L0_HIGH                       ; 1                 ; Untyped                                                                          ;
; L1_HIGH                       ; 1                 ; Untyped                                                                          ;
; G0_HIGH                       ; 1                 ; Untyped                                                                          ;
; G1_HIGH                       ; 1                 ; Untyped                                                                          ;
; G2_HIGH                       ; 1                 ; Untyped                                                                          ;
; G3_HIGH                       ; 1                 ; Untyped                                                                          ;
; E0_HIGH                       ; 1                 ; Untyped                                                                          ;
; E1_HIGH                       ; 1                 ; Untyped                                                                          ;
; E2_HIGH                       ; 1                 ; Untyped                                                                          ;
; E3_HIGH                       ; 1                 ; Untyped                                                                          ;
; L0_LOW                        ; 1                 ; Untyped                                                                          ;
; L1_LOW                        ; 1                 ; Untyped                                                                          ;
; G0_LOW                        ; 1                 ; Untyped                                                                          ;
; G1_LOW                        ; 1                 ; Untyped                                                                          ;
; G2_LOW                        ; 1                 ; Untyped                                                                          ;
; G3_LOW                        ; 1                 ; Untyped                                                                          ;
; E0_LOW                        ; 1                 ; Untyped                                                                          ;
; E1_LOW                        ; 1                 ; Untyped                                                                          ;
; E2_LOW                        ; 1                 ; Untyped                                                                          ;
; E3_LOW                        ; 1                 ; Untyped                                                                          ;
; L0_INITIAL                    ; 1                 ; Untyped                                                                          ;
; L1_INITIAL                    ; 1                 ; Untyped                                                                          ;
; G0_INITIAL                    ; 1                 ; Untyped                                                                          ;
; G1_INITIAL                    ; 1                 ; Untyped                                                                          ;
; G2_INITIAL                    ; 1                 ; Untyped                                                                          ;
; G3_INITIAL                    ; 1                 ; Untyped                                                                          ;
; E0_INITIAL                    ; 1                 ; Untyped                                                                          ;
; E1_INITIAL                    ; 1                 ; Untyped                                                                          ;
; E2_INITIAL                    ; 1                 ; Untyped                                                                          ;
; E3_INITIAL                    ; 1                 ; Untyped                                                                          ;
; L0_MODE                       ; BYPASS            ; Untyped                                                                          ;
; L1_MODE                       ; BYPASS            ; Untyped                                                                          ;
; G0_MODE                       ; BYPASS            ; Untyped                                                                          ;
; G1_MODE                       ; BYPASS            ; Untyped                                                                          ;
; G2_MODE                       ; BYPASS            ; Untyped                                                                          ;
; G3_MODE                       ; BYPASS            ; Untyped                                                                          ;
; E0_MODE                       ; BYPASS            ; Untyped                                                                          ;
; E1_MODE                       ; BYPASS            ; Untyped                                                                          ;
; E2_MODE                       ; BYPASS            ; Untyped                                                                          ;
; E3_MODE                       ; BYPASS            ; Untyped                                                                          ;
; L0_PH                         ; 0                 ; Untyped                                                                          ;
; L1_PH                         ; 0                 ; Untyped                                                                          ;
; G0_PH                         ; 0                 ; Untyped                                                                          ;
; G1_PH                         ; 0                 ; Untyped                                                                          ;
; G2_PH                         ; 0                 ; Untyped                                                                          ;
; G3_PH                         ; 0                 ; Untyped                                                                          ;
; E0_PH                         ; 0                 ; Untyped                                                                          ;
; E1_PH                         ; 0                 ; Untyped                                                                          ;
; E2_PH                         ; 0                 ; Untyped                                                                          ;
; E3_PH                         ; 0                 ; Untyped                                                                          ;
; M_PH                          ; 0                 ; Untyped                                                                          ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                                                                          ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                                                                          ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                                                                          ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                                                                          ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                                                                          ;
; CLK0_COUNTER                  ; G0                ; Untyped                                                                          ;
; CLK1_COUNTER                  ; G0                ; Untyped                                                                          ;
; CLK2_COUNTER                  ; G0                ; Untyped                                                                          ;
; CLK3_COUNTER                  ; G0                ; Untyped                                                                          ;
; CLK4_COUNTER                  ; G0                ; Untyped                                                                          ;
; CLK5_COUNTER                  ; G0                ; Untyped                                                                          ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                                                                          ;
; M_TIME_DELAY                  ; 0                 ; Untyped                                                                          ;
; N_TIME_DELAY                  ; 0                 ; Untyped                                                                          ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                                                                          ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                                                                          ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                                                                          ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                                                                          ;
; ENABLE0_COUNTER               ; L0                ; Untyped                                                                          ;
; ENABLE1_COUNTER               ; L0                ; Untyped                                                                          ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                                                          ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                                                          ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                                                                          ;
; VCO_POST_SCALE                ; 0                 ; Untyped                                                                          ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                                          ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                                          ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                                                          ;
; INTENDED_DEVICE_FAMILY        ; Stratix           ; Untyped                                                                          ;
; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                                                          ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                                                                          ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                                                                          ;
; DEVICE_FAMILY                 ; Stratix           ; Untyped                                                                          ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                                                       ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                                                                     ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                                                                     ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                                                                   ;
+-------------------------------+-------------------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst ;
+----------------+----------+-----------------------------------------------------------------------------+
; Parameter Name ; Value    ; Type                                                                        ;
+----------------+----------+-----------------------------------------------------------------------------+
; f_clk          ; 30000000 ; Integer                                                                     ;
+----------------+----------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                    ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
; LPM_WIDTH               ; 9           ; Integer                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Integer                                                                                 ;
; LPM_WIDTHU              ; 6           ; Integer                                                                                 ;
; LPM_SHOWAHEAD           ; ON          ; Untyped                                                                                 ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
; USE_EAB                 ; ON          ; Untyped                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                                 ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
; DEVICE_FAMILY           ; Stratix     ; Untyped                                                                                 ;
; CBXI_PARAMETER          ; dcfifo_4941 ; Untyped                                                                                 ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel ;
+-------------------------+---------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value   ; Type                                                                                                                                         ;
+-------------------------+---------+----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON      ; AUTO_CARRY                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF     ; IGNORE_CARRY                                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON      ; AUTO_CASCADE                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF     ; IGNORE_CASCADE                                                                                                                               ;
; lpm_width               ; 9       ; Untyped                                                                                                                                      ;
; LPM_NUMWORDS            ; 3       ; Untyped                                                                                                                                      ;
; LPM_WIDTHU              ; 2       ; Untyped                                                                                                                                      ;
; LPM_SHOWAHEAD           ; ON      ; Untyped                                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON      ; Untyped                                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON      ; Untyped                                                                                                                                      ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF     ; Untyped                                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; ON      ; Untyped                                                                                                                                      ;
; ALMOST_FULL_VALUE       ; 0       ; Untyped                                                                                                                                      ;
; ALMOST_EMPTY_VALUE      ; 0       ; Untyped                                                                                                                                      ;
; USE_EAB                 ; OFF     ; Untyped                                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5       ; Untyped                                                                                                                                      ;
; DEVICE_FAMILY           ; Stratix ; Untyped                                                                                                                                      ;
; OPTIMIZE_FOR_SPEED      ; 9       ; Untyped                                                                                                                                      ;
; CBXI_PARAMETER          ; NOTHING ; Untyped                                                                                                                                      ;
+-------------------------+---------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst ;
+-------------------------+------------+---------------------------------------------------------+
; Parameter Name          ; Value      ; Type                                                    ;
+-------------------------+------------+---------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON         ; AUTO_CARRY                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF        ; IGNORE_CARRY                                            ;
; AUTO_CASCADE_CHAINS     ; ON         ; AUTO_CASCADE                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF        ; IGNORE_CASCADE                                          ;
; lpm_width               ; 8          ; Integer                                                 ;
; LPM_NUMWORDS            ; 64         ; Integer                                                 ;
; LPM_WIDTHU              ; 6          ; Integer                                                 ;
; LPM_SHOWAHEAD           ; ON         ; Untyped                                                 ;
; UNDERFLOW_CHECKING      ; ON         ; Untyped                                                 ;
; OVERFLOW_CHECKING       ; ON         ; Untyped                                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF        ; Untyped                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; ON         ; Untyped                                                 ;
; ALMOST_FULL_VALUE       ; 0          ; Untyped                                                 ;
; ALMOST_EMPTY_VALUE      ; 0          ; Untyped                                                 ;
; USE_EAB                 ; ON         ; Untyped                                                 ;
; MAXIMIZE_SPEED          ; 5          ; Untyped                                                 ;
; DEVICE_FAMILY           ; Stratix    ; Untyped                                                 ;
; OPTIMIZE_FOR_SPEED      ; 9          ; Untyped                                                 ;
; CBXI_PARAMETER          ; scfifo_rbn ; Untyped                                                 ;
+-------------------------+------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+--------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                   ;
+------------------------------------+-----------------+--------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                           ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                         ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                                ;
; WIDTH_A                            ; 8               ; Integer                                                ;
; WIDTHAD_A                          ; 6               ; Integer                                                ;
; NUMWORDS_A                         ; 64              ; Integer                                                ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                ;
; WIDTH_B                            ; 1               ; Untyped                                                ;
; WIDTHAD_B                          ; 1               ; Untyped                                                ;
; NUMWORDS_B                         ; 1               ; Untyped                                                ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                                ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                ;
; BYTE_SIZE                          ; 8               ; Untyped                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                                                ;
; CBXI_PARAMETER                     ; altsyncram_k431 ; Untyped                                                ;
+------------------------------------+-----------------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: io_interface:inst|rom_loader:rom_loader_inst ;
+----------------+----------+---------------------------------------------------------------+
; Parameter Name ; Value    ; Type                                                          ;
+----------------+----------+---------------------------------------------------------------+
; f_clk          ; 30000000 ; Integer                                                       ;
; baud_rate      ; 57600    ; Integer                                                       ;
; parity         ; E        ; String                                                        ;
+----------------+----------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3|lpm_or:lpm_or_component ;
+------------------------+---------+--------------------------------------------------------------------------------------+
; Parameter Name         ; Value   ; Type                                                                                 ;
+------------------------+---------+--------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                                                           ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                                                                         ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                                                                         ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                                                                       ;
; LPM_WIDTH              ; 1       ; Integer                                                                              ;
; LPM_SIZE               ; 8       ; Integer                                                                              ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                                                                   ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                                                              ;
; CASCADE_CHAIN          ; MANUAL  ; Untyped                                                                              ;
; DEVICE_FAMILY          ; Stratix ; Untyped                                                                              ;
+------------------------+---------+--------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|lpm_or8:inst20|lpm_or:lpm_or_component ;
+------------------------+---------+---------------------------------------------------------------------------------------------+
; Parameter Name         ; Value   ; Type                                                                                        ;
+------------------------+---------+---------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                                                                              ;
; LPM_WIDTH              ; 1       ; Integer                                                                                     ;
; LPM_SIZE               ; 8       ; Integer                                                                                     ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                                                                          ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                                                                     ;
; CASCADE_CHAIN          ; MANUAL  ; Untyped                                                                                     ;
; DEVICE_FAMILY          ; Stratix ; Untyped                                                                                     ;
+------------------------+---------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DEP-CPU:inst2|lpm_bustri0:8TBUF|lpm_bustri:lpm_bustri_component ;
+----------------+-------+-------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------+
; LPM_WIDTH      ; 8     ; Integer                                                                             ;
+----------------+-------+-------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: RAM:inst4|altsyncram:ram_component ;
+------------------------------------+-----------------+--------------------------+
; Parameter Name                     ; Value           ; Type                     ;
+------------------------------------+-----------------+--------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                  ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE           ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                  ;
; WIDTH_A                            ; 8               ; Integer                  ;
; WIDTHAD_A                          ; 8               ; Integer                  ;
; NUMWORDS_A                         ; 256             ; Integer                  ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                  ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                  ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                  ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                  ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                  ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                  ;
; WIDTH_B                            ; 8               ; Integer                  ;
; WIDTHAD_B                          ; 8               ; Integer                  ;
; NUMWORDS_B                         ; 256             ; Integer                  ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                  ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                  ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                  ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                  ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                  ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                  ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                  ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                  ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                  ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                  ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                  ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                  ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                  ;
; WIDTH_BYTEENA_B                    ; 1               ; Integer                  ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                  ;
; BYTE_SIZE                          ; 8               ; Untyped                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                  ;
; INIT_FILE                          ; INIT/ram.mif    ; Untyped                  ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                  ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                  ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                  ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                  ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                  ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                  ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                  ;
; CBXI_PARAMETER                     ; altsyncram_fe71 ; Untyped                  ;
+------------------------------------+-----------------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component0 ;
+------------------------------------+-----------------+---------------------------+
; Parameter Name                     ; Value           ; Type                      ;
+------------------------------------+-----------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE            ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                   ;
; WIDTH_A                            ; 8               ; Integer                   ;
; WIDTHAD_A                          ; 8               ; Integer                   ;
; NUMWORDS_A                         ; 256             ; Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                   ;
; WIDTH_B                            ; 8               ; Integer                   ;
; WIDTHAD_B                          ; 8               ; Integer                   ;
; NUMWORDS_B                         ; 256             ; Integer                   ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                   ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                   ;
; BYTE_SIZE                          ; 8               ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                   ;
; INIT_FILE                          ; INIT/rom0.mif   ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                   ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_4j91 ; Untyped                   ;
+------------------------------------+-----------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component1 ;
+------------------------------------+-----------------+---------------------------+
; Parameter Name                     ; Value           ; Type                      ;
+------------------------------------+-----------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE            ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                   ;
; WIDTH_A                            ; 8               ; Integer                   ;
; WIDTHAD_A                          ; 8               ; Integer                   ;
; NUMWORDS_A                         ; 256             ; Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                   ;
; WIDTH_B                            ; 8               ; Integer                   ;
; WIDTHAD_B                          ; 8               ; Integer                   ;
; NUMWORDS_B                         ; 256             ; Integer                   ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                   ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                   ;
; BYTE_SIZE                          ; 8               ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                   ;
; INIT_FILE                          ; INIT/rom1.mif   ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                   ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_5j91 ; Untyped                   ;
+------------------------------------+-----------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component2 ;
+------------------------------------+-----------------+---------------------------+
; Parameter Name                     ; Value           ; Type                      ;
+------------------------------------+-----------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE            ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                   ;
; WIDTH_A                            ; 8               ; Integer                   ;
; WIDTHAD_A                          ; 8               ; Integer                   ;
; NUMWORDS_A                         ; 256             ; Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                   ;
; WIDTH_B                            ; 8               ; Integer                   ;
; WIDTHAD_B                          ; 8               ; Integer                   ;
; NUMWORDS_B                         ; 256             ; Integer                   ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                   ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                   ;
; BYTE_SIZE                          ; 8               ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                   ;
; INIT_FILE                          ; INIT/rom2.mif   ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                   ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_6j91 ; Untyped                   ;
+------------------------------------+-----------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ROM:inst1|altsyncram:rom_component3 ;
+------------------------------------+-----------------+---------------------------+
; Parameter Name                     ; Value           ; Type                      ;
+------------------------------------+-----------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE            ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                   ;
; WIDTH_A                            ; 8               ; Integer                   ;
; WIDTHAD_A                          ; 8               ; Integer                   ;
; NUMWORDS_A                         ; 256             ; Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                   ;
; WIDTH_B                            ; 8               ; Integer                   ;
; WIDTHAD_B                          ; 8               ; Integer                   ;
; NUMWORDS_B                         ; 256             ; Integer                   ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                   ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                   ;
; BYTE_SIZE                          ; 8               ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                   ;
; INIT_FILE                          ; INIT/rom3.mif   ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                   ;
; DEVICE_FAMILY                      ; Stratix         ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_7j91 ; Untyped                   ;
+------------------------------------+-----------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                                    ;
+----------------------------+------------------------------------------------------------------------------------+
; Name                       ; Value                                                                              ;
+----------------------------+------------------------------------------------------------------------------------+
; Number of entity instances ; 1                                                                                  ;
; Entity Instance            ; io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                         ;
;     -- LPM_WIDTH           ; 9                                                                                  ;
;     -- LPM_NUMWORDS        ; 64                                                                                 ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                 ;
;     -- USE_EAB             ; ON                                                                                 ;
+----------------------------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                                                                     ;
+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                               ;
+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                                                                   ;
; Entity Instance            ; io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel ;
;     -- FIFO Type           ; Single Clock                                                                                                                        ;
;     -- lpm_width           ; 9                                                                                                                                   ;
;     -- LPM_NUMWORDS        ; 3                                                                                                                                   ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                                                                  ;
;     -- USE_EAB             ; OFF                                                                                                                                 ;
; Entity Instance            ; io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst                                                                                   ;
;     -- FIFO Type           ; Single Clock                                                                                                                        ;
;     -- lpm_width           ; 8                                                                                                                                   ;
;     -- LPM_NUMWORDS        ; 64                                                                                                                                  ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                                                                  ;
;     -- USE_EAB             ; ON                                                                                                                                  ;
+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/dep-cpu_vorlage/DEP-CPU.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Jul 17 15:19:13 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DEP-CPU -c DEP-CPU
Info: Found 1 design units, including 1 entities, in source file Alu_Test.bdf
    Info: Found entity 1: Alu_Test
Info: Found 1 design units, including 1 entities, in source file Vorlage.bdf
    Info: Found entity 1: Vorlage
Info: Found 2 design units, including 1 entities, in source file ROM.vhd
    Info: Found design unit 1: ROM-r
    Info: Found entity 1: ROM
Info: Found 2 design units, including 1 entities, in source file RAM.vhd
    Info: Found design unit 1: RAM-r
    Info: Found entity 1: RAM
Info: Found 2 design units, including 1 entities, in source file io_interface.vhd
    Info: Found design unit 1: io_interface-ioi
    Info: Found entity 1: io_interface
Info: Found 2 design units, including 1 entities, in source file address_decoder.vhd
    Info: Found design unit 1: address_decoder-ad
    Info: Found entity 1: address_decoder
Info: Found 2 design units, including 1 entities, in source file release_id.vhd
    Info: Found design unit 1: release_id-ri
    Info: Found entity 1: release_id
Info: Found 2 design units, including 1 entities, in source file alu_tester.vhd
    Info: Found design unit 1: alu_tester-at
    Info: Found entity 1: alu_tester
Info: Found 2 design units, including 1 entities, in source file rom_selector.vhd
    Info: Found design unit 1: rom_selector-rs
    Info: Found entity 1: rom_selector
Info: Found 2 design units, including 1 entities, in source file button_interface.vhd
    Info: Found design unit 1: button_interface-bi
    Info: Found entity 1: button_interface
Info: Found 2 design units, including 1 entities, in source file rail_interface.vhd
    Info: Found design unit 1: rail_interface-ri
    Info: Found entity 1: rail_interface
Info: Found 2 design units, including 1 entities, in source file DoubleSevenSegmentDecoder.vhd
    Info: Found design unit 1: DoubleSevenSegmentDecoder-DSSD
    Info: Found entity 1: DoubleSevenSegmentDecoder
Info: Found 2 design units, including 1 entities, in source file seven_segment_interface.vhd
    Info: Found design unit 1: seven_segment_interface-ssi
    Info: Found entity 1: seven_segment_interface
Info: Found 2 design units, including 1 entities, in source file led_interface.vhd
    Info: Found design unit 1: led_interface-li
    Info: Found entity 1: led_interface
Info: Found 2 design units, including 1 entities, in source file display_interface.vhd
    Info: Found design unit 1: display_interface-di
    Info: Found entity 1: display_interface
Info: Found 2 design units, including 1 entities, in source file fifo.vhd
    Info: Found design unit 1: fifo-f
    Info: Found entity 1: fifo
Info: Found 2 design units, including 1 entities, in source file lifo.vhd
    Info: Found design unit 1: lifo-l
    Info: Found entity 1: lifo
Info: Found 2 design units, including 1 entities, in source file main_pll_configurable.vhd
    Info: Found design unit 1: main_pll_configurable-mpc
    Info: Found entity 1: main_pll_configurable
Info: Found 2 design units, including 1 entities, in source file counters.vhd
    Info: Found design unit 1: counters-c
    Info: Found entity 1: counters
Info: Found 2 design units, including 1 entities, in source file rom_loader.vhd
    Info: Found design unit 1: rom_loader-rl
    Info: Found entity 1: rom_loader
Info: Found 1 design units, including 1 entities, in source file halbaddierer_mtwo.bdf
    Info: Found entity 1: halbaddierer_mtwo
Info: Found 1 design units, including 1 entities, in source file volladdierer_mtwo.bdf
    Info: Found entity 1: volladdierer_mtwo
Info: Found 1 design units, including 1 entities, in source file 8bitaddierer_subtrahierer_mtwo.bdf
    Info: Found entity 1: 8bitaddierer_subtrahierer_mtwo
Info: Found 1 design units, including 1 entities, in source file incrim_mtwo.bdf
    Info: Found entity 1: incrim_mtwo
Info: Found 1 design units, including 1 entities, in source file multiplexer_mtwo.bdf
    Info: Found entity 1: multiplexer_mtwo
Info: Found 1 design units, including 1 entities, in source file 8bitmultiplexer_mtwo.bdf
    Info: Found entity 1: 8bitmultiplexer_mtwo
Info: Found 1 design units, including 1 entities, in source file registeren_2bit.bdf
    Info: Found entity 1: registeren_2bit
Info: Found 1 design units, including 1 entities, in source file register_2bit.bdf
    Info: Found entity 1: register_2bit
Info: Found 1 design units, including 1 entities, in source file registeren_8bit.bdf
    Info: Found entity 1: registeren_8bit
Info: Found 1 design units, including 1 entities, in source file register_2bit_reset.bdf
    Info: Found entity 1: register_2bit_reset
Info: Found 1 design units, including 1 entities, in source file registeren_8bit_reset.bdf
    Info: Found entity 1: registeren_8bit_reset
Info: Found 1 design units, including 1 entities, in source file DEP-CPU.bdf
    Info: Found entity 1: DEP-CPU
Info: Found 1 design units, including 1 entities, in source file decoder.bdf
    Info: Found entity 1: decoder
Info: Found 1 design units, including 1 entities, in source file ALU.bdf
    Info: Found entity 1: ALU
Info: Found 1 design units, including 1 entities, in source file multiALU.bdf
    Info: Found entity 1: multiALU
Info: Found 1 design units, including 1 entities, in source file 2bitmultiplexer_mtwo.bdf
    Info: Found entity 1: 2bitmultiplexer_mtwo
Info: Found 1 design units, including 1 entities, in source file ALU_logik.bdf
    Info: Found entity 1: ALU_logik
Info: Found 1 design units, including 1 entities, in source file ALU_arithmetik.bdf
    Info: Found entity 1: ALU_arithmetik
Info: Found 1 design units, including 1 entities, in source file decoder_backup.bdf
    Info: Found entity 1: decoder_backup
Info: Elaborating entity "Vorlage" for the top level hierarchy
Info: Elaborating entity "io_interface" for hierarchy "io_interface:inst"
Info: Elaborating entity "main_pll_configurable" for hierarchy "io_interface:inst|main_pll_configurable:main_pll_configurable_inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "io_interface:inst|main_pll_configurable:main_pll_configurable_inst|altpll:main_pll_inst"
Info: Elaborating entity "address_decoder" for hierarchy "io_interface:inst|address_decoder:address_decoder_inst"
Info: Elaborating entity "seven_segment_interface" for hierarchy "io_interface:inst|seven_segment_interface:seven_segment_interface_inst"
Info: Elaborating entity "DoubleSevenSegmentDecoder" for hierarchy "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|DoubleSevenSegmentDecoder:double_ss_dec"
Info: Elaborating entity "rail_interface" for hierarchy "io_interface:inst|rail_interface:rail_interface_inst"
Info: Elaborating entity "button_interface" for hierarchy "io_interface:inst|button_interface:button_interface_inst"
Info: Elaborating entity "led_interface" for hierarchy "io_interface:inst|led_interface:led_interface_inst"
Info: Elaborating entity "display_interface" for hierarchy "io_interface:inst|display_interface:display_interface_inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Elaborating entity "dcfifo" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_4941.tdf
    Info: Found entity 1: dcfifo_4941
Info: Elaborating entity "dcfifo_4941" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_k5b.tdf
    Info: Found entity 1: a_gray2bin_k5b
Info: Elaborating entity "a_gray2bin_k5b" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_gray2bin_k5b:read_side_gray_converter"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_i16.tdf
    Info: Found entity 1: a_graycounter_i16
Info: Elaborating entity "a_graycounter_i16" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_graycounter_i16:rdptr_g"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j16.tdf
    Info: Found entity 1: a_graycounter_j16
Info: Elaborating entity "a_graycounter_j16" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|a_graycounter_j16:read_counter_for_write"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l1v.tdf
    Info: Found entity 1: altsyncram_l1v
Info: Elaborating entity "altsyncram_l1v" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|altsyncram_l1v:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lc8.tdf
    Info: Found entity 1: alt_synch_pipe_lc8
Info: Elaborating entity "alt_synch_pipe_lc8" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf
    Info: Found entity 1: dffpipe_fd9
Info: Elaborating entity "dffpipe_fd9" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_lc8:read_sync_registers|dffpipe_fd9:dffpipe10"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_mc8.tdf
    Info: Found entity 1: alt_synch_pipe_mc8
Info: Elaborating entity "alt_synch_pipe_mc8" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
    Info: Found entity 1: dffpipe_gd9
Info: Elaborating entity "dffpipe_gd9" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|alt_synch_pipe_mc8:write_sync_registers|dffpipe_gd9:dffpipe14"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_avb.tdf
    Info: Found entity 1: add_sub_avb
Info: Elaborating entity "add_sub_avb" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|add_sub_avb:rdusedw_subtractor"
Info: Found 1 design units, including 1 entities, in source file db/cntr_uv7.tdf
    Info: Found entity 1: cntr_uv7
Info: Elaborating entity "cntr_uv7" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|cntr_uv7:rdptr_b"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_f2fifo.tdf
    Info: Found entity 1: a_f2fifo
Info: Elaborating entity "a_f2fifo" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_counter:usedw_ptr"
Info: Found 1 design units, including 1 entities, in source file db/cntr_g1b.tdf
    Info: Found entity 1: cntr_g1b
Info: Elaborating entity "cntr_g1b" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_counter:usedw_ptr|cntr_g1b:auto_generated"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00002"
Info: Elaborating entity "lpm_ff" for hierarchy "io_interface:inst|display_interface:display_interface_inst|dcfifo:dcfifo_component|dcfifo_4941:auto_generated|scfifo:output_channel|a_f2fifo:subfifo|lpm_ff:$00010"
Info: Elaborating entity "fifo" for hierarchy "io_interface:inst|fifo:fifo_inst"
Info: Elaborating entity "scfifo" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_rbn.tdf
    Info: Found entity 1: scfifo_rbn
Info: Elaborating entity "scfifo_rbn" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_a3n.tdf
    Info: Found entity 1: a_dpfifo_a3n
Info: Elaborating entity "a_dpfifo_a3n" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vh11.tdf
    Info: Found entity 1: altsyncram_vh11
Info: Elaborating entity "altsyncram_vh11" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|altsyncram_vh11:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cntr_se8.tdf
    Info: Found entity 1: cntr_se8
Info: Elaborating entity "cntr_se8" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_se8:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_bd7.tdf
    Info: Found entity 1: cntr_bd7
Info: Elaborating entity "cntr_bd7" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_bd7:usedw_counter"
Info: Found 1 design units, including 1 entities, in source file db/cntr_te8.tdf
    Info: Found entity 1: cntr_te8
Info: Elaborating entity "cntr_te8" for hierarchy "io_interface:inst|fifo:fifo_inst|scfifo:fifo_inst|scfifo_rbn:auto_generated|a_dpfifo_a3n:dpfifo|cntr_te8:wr_ptr"
Info: Elaborating entity "lifo" for hierarchy "io_interface:inst|lifo:lifo_inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_k431.tdf
    Info: Found entity 1: altsyncram_k431
Info: Elaborating entity "altsyncram_k431" for hierarchy "io_interface:inst|lifo:lifo_inst|altsyncram:altsyncram_component|altsyncram_k431:auto_generated"
Info: Elaborating entity "rom_selector" for hierarchy "io_interface:inst|rom_selector:rom_selector_inst"
Info: Elaborating entity "release_id" for hierarchy "io_interface:inst|release_id:release_id_inst"
Info: Elaborating entity "counters" for hierarchy "io_interface:inst|counters:counters_inst"
Info: Elaborating entity "rom_loader" for hierarchy "io_interface:inst|rom_loader:rom_loader_inst"
Info: Elaborating entity "DEP-CPU" for hierarchy "DEP-CPU:inst2"
Info: Elaborating entity "decoder" for hierarchy "DEP-CPU:inst2|decoder:Decoder"
Warning: Primitive "NOT" of instance "inst22" not used
Warning: Primitive "NOT" of instance "inst23" not used
Warning: Primitive "AND4" of instance "inst35" not used
Warning: Primitive "AND4" of instance "inst36" not used
Warning: Primitive "AND2" of instance "inst37" not used
Warning: Primitive "OR3" of instance "inst38" not used
Warning: Primitive "AND3" of instance "inst43" not used
Warning: Primitive "AND3" of instance "inst44" not used
Warning: Primitive "AND2" of instance "inst45" not used
Warning: Primitive "OR3" of instance "inst46" not used
Warning: Primitive "AND4" of instance "inst52" not used
Warning: Primitive "AND4" of instance "inst53" not used
Warning: Primitive "AND2" of instance "inst54" not used
Warning: Primitive "OR3" of instance "inst55" not used
Warning: Primitive "AND3" of instance "inst59" not used
Warning: Primitive "OR2" of instance "inst60" not used
Info: Elaborating entity "registeren_2bit" for hierarchy "DEP-CPU:inst2|registeren_2bit:CCR"
Info: Elaborating entity "ALU" for hierarchy "DEP-CPU:inst2|ALU:ALU"
Info: Elaborating entity "8bitmultiplexer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|8bitmultiplexer_mtwo:inst2"
Info: Elaborating entity "ALU_logik" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst"
Warning: Using design file 8bitOr.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: 8bitOr
Info: Elaborating entity "8bitOr" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|8bitOr:inst12"
Warning: Using design file 8bitXOr.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: 8bitXOr
Info: Elaborating entity "8bitXOr" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|8bitXOr:inst13"
Warning: Using design file 8bitAnd.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: 8bitAnd
Info: Elaborating entity "8bitAnd" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|8bitAnd:inst"
Warning: Using design file lpm_or8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_or8-SYN
    Info: Found entity 1: lpm_or8
Info: Elaborating entity "lpm_or8" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_or.tdf
    Info: Found entity 1: lpm_or
Info: Elaborating entity "lpm_or" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_logik:inst|lpm_or8:inst3|lpm_or:lpm_or_component"
Info: Elaborating entity "ALU_arithmetik" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1"
Info: Elaborating entity "8bitaddierer_subtrahierer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17"
Info: Elaborating entity "volladdierer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst8"
Info: Elaborating entity "halbaddierer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|8bitaddierer_subtrahierer_mtwo:inst17|volladdierer_mtwo:inst8|halbaddierer_mtwo:inst"
Info: Elaborating entity "2bitmultiplexer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|2bitmultiplexer_mtwo:inst14"
Info: Elaborating entity "multiplexer_mtwo" for hierarchy "DEP-CPU:inst2|ALU:ALU|ALU_arithmetik:inst1|multiplexer_mtwo:inst18"
Info: Elaborating entity "registeren_8bit" for hierarchy "DEP-CPU:inst2|registeren_8bit:ACCR"
Info: Elaborating entity "register_2bit" for hierarchy "DEP-CPU:inst2|register_2bit:MSR"
Info: Elaborating entity "registeren_8bit_reset" for hierarchy "DEP-CPU:inst2|registeren_8bit_reset:PCR"
Info: Elaborating entity "incrim_mtwo" for hierarchy "DEP-CPU:inst2|incrim_mtwo:inst"
Warning: Using design file lpm_bustri0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_bustri0-SYN
    Info: Found entity 1: lpm_bustri0
Info: Elaborating entity "lpm_bustri0" for hierarchy "DEP-CPU:inst2|lpm_bustri0:8TBUF"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf
    Info: Found entity 1: lpm_bustri
Info: Elaborating entity "lpm_bustri" for hierarchy "DEP-CPU:inst2|lpm_bustri0:8TBUF|lpm_bustri:lpm_bustri_component"
Info: Elaborating entity "RAM" for hierarchy "RAM:inst4"
Info: Elaborating entity "altsyncram" for hierarchy "RAM:inst4|altsyncram:ram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fe71.tdf
    Info: Found entity 1: altsyncram_fe71
Info: Elaborating entity "altsyncram_fe71" for hierarchy "RAM:inst4|altsyncram:ram_component|altsyncram_fe71:auto_generated"
Info: Elaborating entity "ROM" for hierarchy "ROM:inst1"
Info: Elaborating entity "altsyncram" for hierarchy "ROM:inst1|altsyncram:rom_component0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4j91.tdf
    Info: Found entity 1: altsyncram_4j91
Info: Elaborating entity "altsyncram_4j91" for hierarchy "ROM:inst1|altsyncram:rom_component0|altsyncram_4j91:auto_generated"
Info: Elaborating entity "altsyncram" for hierarchy "ROM:inst1|altsyncram:rom_component1"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5j91.tdf
    Info: Found entity 1: altsyncram_5j91
Info: Elaborating entity "altsyncram_5j91" for hierarchy "ROM:inst1|altsyncram:rom_component1|altsyncram_5j91:auto_generated"
Info: Elaborating entity "altsyncram" for hierarchy "ROM:inst1|altsyncram:rom_component2"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6j91.tdf
    Info: Found entity 1: altsyncram_6j91
Info: Elaborating entity "altsyncram_6j91" for hierarchy "ROM:inst1|altsyncram:rom_component2|altsyncram_6j91:auto_generated"
Info: Elaborating entity "altsyncram" for hierarchy "ROM:inst1|altsyncram:rom_component3"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7j91.tdf
    Info: Found entity 1: altsyncram_7j91
Info: Elaborating entity "altsyncram_7j91" for hierarchy "ROM:inst1|altsyncram:rom_component3|altsyncram_7j91:auto_generated"
Info: State machine "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state" contains 5 states
Info: State machine "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode" contains 4 states
Info: State machine "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode" contains 8 states
Info: State machine "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state"
Info: Encoding result for state machine "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "io_interface:inst|display_interface:display_interface_inst|state.ok"
        Info: Encoded state bit "io_interface:inst|display_interface:display_interface_inst|state.after_3rd_reset"
        Info: Encoded state bit "io_interface:inst|display_interface:display_interface_inst|state.after_2nd_reset"
        Info: Encoded state bit "io_interface:inst|display_interface:display_interface_inst|state.after_1st_reset"
        Info: Encoded state bit "io_interface:inst|display_interface:display_interface_inst|state.wait_power_up"
    Info: State "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state.wait_power_up" uses code string "00000"
    Info: State "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state.after_1st_reset" uses code string "00011"
    Info: State "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state.after_2nd_reset" uses code string "00101"
    Info: State "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state.after_3rd_reset" uses code string "01001"
    Info: State "|Vorlage|io_interface:inst|display_interface:display_interface_inst|state.ok" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode"
Info: Encoding result for state machine "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "io_interface:inst|led_interface:led_interface_inst|mode.show_nothing"
        Info: Encoded state bit "io_interface:inst|led_interface:led_interface_inst|mode.show_custom_data"
        Info: Encoded state bit "io_interface:inst|led_interface:led_interface_inst|mode.show_data_bus"
        Info: Encoded state bit "io_interface:inst|led_interface:led_interface_inst|mode.show_address_bus"
    Info: State "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode.show_address_bus" uses code string "0000"
    Info: State "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode.show_data_bus" uses code string "0011"
    Info: State "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode.show_custom_data" uses code string "0101"
    Info: State "|Vorlage|io_interface:inst|led_interface:led_interface_inst|mode.show_nothing" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode"
Info: Encoding result for state machine "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_nothing"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_segments_right"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_segments_left"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_rail_info"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_ram_monitor"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_hex"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_address_bus"
        Info: Encoded state bit "io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_data_bus"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_data_bus" uses code string "00000000"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_address_bus" uses code string "00000011"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_hex" uses code string "00000101"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_ram_monitor" uses code string "00001001"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_rail_info" uses code string "00010001"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_segments_left" uses code string "00100001"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_custom_segments_right" uses code string "01000001"
    Info: State "|Vorlage|io_interface:inst|seven_segment_interface:seven_segment_interface_inst|mode.show_nothing" uses code string "10000001"
Info: Selected Auto state machine encoding method for state machine "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode"
Info: Encoding result for state machine "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.external_once"
        Info: Encoded state bit "io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.external"
        Info: Encoded state bit "io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.software"
        Info: Encoded state bit "io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.parameter"
    Info: State "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.parameter" uses code string "0000"
    Info: State "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.software" uses code string "0011"
    Info: State "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.external" uses code string "0101"
    Info: State "|Vorlage|io_interface:inst|main_pll_configurable:main_pll_configurable_inst|speed_step_mode.external_once" uses code string "1001"
Warning: Converting TRI node "io_interface:inst|data_bus~9" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~13" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~17" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~21" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~25" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~29" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~33" that feeds logic to an OR gate
Warning: Converting TRI node "io_interface:inst|data_bus~37" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[7]~749" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[6]~753" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[5]~757" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[4]~761" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[3]~765" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[2]~769" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[1]~773" that feeds logic to an OR gate
Warning: Converting TRI node "ROM:inst1|data[0]~777" that feeds logic to an OR gate
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "reconfig_n" stuck at VCC
    Warning: Pin "console_dcd" stuck at GND
    Warning: Pin "console_rxd" stuck at GND
    Warning: Pin "console_dsr" stuck at GND
    Warning: Pin "console_cts" stuck at GND
    Warning: Pin "console_ri" stuck at GND
    Warning: Pin "debug_dcd" stuck at GND
    Warning: Pin "debug_rxd" stuck at GND
    Warning: Pin "debug_dsr" stuck at GND
    Warning: Pin "debug_cts" stuck at GND
    Warning: Pin "debug_ri" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Design contains 5 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "console_dtr"
    Warning: No output dependent on input pin "console_rts"
    Warning: No output dependent on input pin "debug_txd"
    Warning: No output dependent on input pin "debug_dtr"
    Warning: No output dependent on input pin "debug_rts"
Info: Implemented 1730 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 43 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 1596 logic cells
    Info: Implemented 65 RAM segments
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings
    Info: Processing ended: Mon Jul 17 15:19:57 2006
    Info: Elapsed time: 00:00:44


