The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.vhd. The design altpll0.vhd has Stratix AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted.